3 Charge Pump Jobs

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Youzentech Technologies is currently seeking an experienced Analog IC Layout Engineer to be a part of our team in Hyderabad. If you possess 5-10 years of expertise in Custom Mixed-Signal Layout Design, we are eager to hear from you. The position is based in Hyderabad/Bangalore and requires the following qualifications and responsibilities: - Proficiency in Full Custom & Semi-Custom Analog IP & IC Layout, starting from schematic to verification - Hands-on experience with various components including Temperature Sensor, SerDes, PLL, ADC, DAC, LDO, Bandgap, Charge Pump, Current Mirrors, Differential Amplifier, and more - Skilled in LVS/DRC debugging & verification for 16FF and below nodes (TSMC, Samsung, GF) - Strong understanding of EM, ESD, Shielding, Parasitic, and Layout-dependent effects - Familiarity with Cadence, Calibre, Assura, Redhawk, and Totem for verification purposes - Experience in supporting multiple Tape-outs and collaborating with cross-functional teams - Knowledge of Layout automation (SKILL/PERL) would be an added advantage - Mandatory experience with TSMC 7nm technology If you meet the requirements and are interested in this opportunity, please share your resume with us at amith.m@youzentech.com.,

Role & responsibilities Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Ability to understand design hierarchy and different architectures for Memory designs. Excellent command and problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Prefer to have expertise in PERL/SHELL/SKILL. Experience of Virtuoso, IC compiler, Finesim, ANSYS Totem, and Signal Integrity is advantageous. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent verbal and written communication skills.