5.0 - 9.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this position should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. Additionally, a minimum of 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR) is required. You should have expertise in silicon bringup, functional validation, characterizing, and qualification, along with experience in board schematics, layout, and debug methodologies using lab equipment. Preferred qualifications include experience in hardware emulation with hardware/software integration, proficiency in coding languages (e.g., Python) for automation development, and familiarity with Register-Transfer Level (RTL) design, verification, or emulation. Knowledge of SoC architecture, including boot flows, and understanding of HBM/DDR standards would be advantageous. As a member of this team, you will contribute to shaping the future of AI/ML hardware acceleration by working on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your role will involve verifying complex digital designs, specifically focusing on TPU architecture and its integration within AI/ML-driven systems. You will be responsible for the post-silicon validation of the Cloud Tensor Processing Unit (TPU) projects. This includes creating test plans and test content, executing tests on pre-silicon and post-silicon platforms, as well as debugging and troubleshooting issues. Collaboration with engineers from various teams will be essential to validate the functional, power, performance, and electrical characteristics of the Cloud TPU silicon. The ML, Systems, & Cloud AI (MSCA) organization at Google is dedicated to designing and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team aims to shape the future of hyperscale computing. Key responsibilities for this role include developing and executing tests for memory controller High Bandwidth Memory (HBM) post-silicon validation, driving debugging efforts, ensuring necessary functional coverage for skilled design, and assisting in the operation and maintenance of the hardware emulation platform. If you are passionate about AI/ML hardware acceleration and eager to contribute to innovative projects that impact millions worldwide, this role offers an exciting opportunity to be part of a team that pushes boundaries and develops custom silicon solutions for Google's TPU technology.,

Posted 14 hours ago

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