4.0 - 12.0 years

0 Lacs

karnataka

On-site

Job Description: You are required to have 4-12+ years of experience in FEINT (front end integration) with skills in RTL linting, CDC/RDC checks, logic synthesis, and LEC in ECO context. Key Responsibilities: - Work as an RTL Design Lead - Conduct RTL linting and CDC/RDC checks - Perform logic synthesis - Execute LEC in ECO context Qualifications Required: - 4-12+ years of experience in FEINT - Proficiency in RTL linting, CDC/RDC checks, logic synthesis, and LEC in ECO context Please share your resume to jayalakshmi.r2@ust.com.,

Posted 1 month ago

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ASIC Digital Design Engr, Staff Synopsys

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As an ASIC Digital Design Engineer, Design Lead at Synopsys, you will be at the forefront of driving innovations that revolutionize the way we work and play. From self-driving cars to artificial intelligence, from the cloud to 5G and the Internet of Things, we are powering the Era of Smart Everything with cutting-edge technologies for chip design and software security. If you are passionate about innovation, we are excited to meet you. Our Silicon IP Subsystems business focuses on accelerating the integration of capabilities into System on Chips (SoCs). With the widest range of silicon IP offerings including logic, memory, interfaces, analog, security, and embedded processors, we help custom...

Posted 3 months ago

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