452 Cdc Jobs - Page 10

About Medblocks Medblocks is building a developer-focused ?stack for healthcare? that makes it possible for anyone to build applications that integrate directly with clinical workflows without rebuilding expensive Electronic Medical Records systems We believe code has the potential to save more lives than doctors can by themselves Founded by doctors-turned-programmers, our team leverages open, vendor-neutral standards like openEHR, FHIR, SMART, and SNOMED CT to create a platform that makes healthcare data accessible, interoperable, and useful Our Culture Were a remote-first team that values deep work, clear communication, and continuous learning Were building technology that matters, and wer...

Executive Chef - European or Continetal - Kolkata - 15 LPA. Age max 40 yrs. Min 10 yrs exp in only Continental /European Cuisine reqd. Min 2 yrs as Executive Chef is must. Hotel Mgmt reqd. Excellent Communication skills must. Overseas Exp preferred.

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5...

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: At least 5yrs of industry experience Experience with RTL front-end tools like RDC, CDC, Lint etc. Experience with writing and validating synthesis constraints. Experience with scripting like Perl, python, TCL etc. Experience Required: 5 + Years TekWissen Group is an equal opportunity employer supporting workforce diversity.

Detailed description: Key Objectives of this Role: Perform System Architecture activities for Infotainment, Telematics and Cluster Products in Compliance to ASPICE standards Perform System Architecture analysis based on customer requirements and capture the system architecture in compliance with applicable automotive standards End to End detailed knowledge on Vehicle Interface Processor, SOC, TCU, MODEM, BT-WiFi, Serializer, De-Serializer, DSP, Amplifier, Encoder, Decoder, Memory and its relevant interfaces and applications. Identify the System Elements and Its interaction/Interfaces to deliver the defined Product features. Perform the expected System Resource Estimations and Optimize as req...

We are looking for a highly skilled and experienced Analyst to join our team at eClerx Services Ltd. The ideal candidate will have a strong background in IT Services & Consulting, with excellent analytical skills and attention to detail. Roles and Responsibility Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain complex data analysis systems and reports. Provide expert-level support for data analysis and reporting needs. Identify trends and patterns in large datasets to inform business decisions. Develop and implement process improvements to increase efficiency and productivity. Communicate findings and insights to stakeholders throu...

Role & responsibilities Must have exposure to NoC, IP/ SoC Design, CDC, AXI, Bus Interconnects

The people are the culture. We encourage a culture of passion for technology solutions that impact businesses. We also make sure that our people pursue their individual passions. Working with us means you get an in-depth understanding of a range of industries and emerging technologies that help us build solutions that are futuristic and impactful. More importantly, the experience of being at MarvyLogic may help you evolve as a person toward enjoying a more fulfilling life. Minimum BE/BS degree in Electrical/Electronics/Computer science required. At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts. Experience in physic...

You have an immediate job opening with one of your valuable clients in Hyderabad for FPGA with Firmware profiles. The ideal candidate should have at least 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is Hyderabad and the notice period is immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call +919900927620 for further discussion.,

The ASIC/SOC Front End Design Engineer role involves setting up ASIC QA flows for RTL design quality checks, understanding top-level interfaces, clock structure, reset structure, RAMs, CDC boundaries, and power domains. You will be responsible for executing various design steps such as Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, and CLP. Additionally, you will create clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers while reviewing flow errors, design errors, and violations. As an ASIC/SOC Front End Design Engineer, you will debug CDC and RDC issues, provide RTL fixes, and support the DFX team for DFX controller integration, Scan insertion...

Job Details Job Description: Part of the global PCIe/CXL Center of Excellent (CoE) team, developing the latest & state of the art PCIe/CXL solution for next generation FPGA in the latest process technology node. Develops logic/RTL design and simulation for IP/SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Works with IP providers to integrate and validate IPs at the SoC level. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timi...

Who We Are Boston Consulting Group partners with leaders in business and society to tackle their most important challenges and capture their greatest opportunities. BCG was the pioneer in business strategy when it was founded in 1963. Today, we help clients with total transformation-inspiring complex change, enabling organizations to grow, building competitive advantage, and driving bottom-line impact. To succeed, organizations must blend digital and human capabilities. Our diverse, global teams bring deep industry and functional expertise and a range of perspectives to spark change. BCG delivers solutions through leading-edge management consulting along with technology and design, corporate...

You should have a Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture, or equivalent practical experience. With 4 years of experience in RTL coding and experience with RTL quality checks methodologies such as Lint, CDC, RDC. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a specialization in computer architecture is preferred. Experience in implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs like Display or Video Codecs would be advantageous. Also, familiarity with ASIC design methodologies for clock domai...

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in usi...

About Medblocks Medblocks is building a developer-focused stack for healthcare that makes it possible for anyone to build applications that integrate directly with clinical workflows without rebuilding expensive Electronic Medical Records systems. We believe code has the potential to save more lives than doctors can by themselves. Founded by doctors-turned-programmers, our team leverages open, vendor-neutral standards like openEHR, FHIR, SMART, and SNOMED CT to create a platform that makes healthcare data accessible, interoperable, and useful. Our Culture At Medblocks, we operate with three core values: Trust: We trust youll get your work done without micromanagement. We dont enforce working...

You are invited to apply for a job opportunity in Bengaluru and Hyderabad if you meet the qualifications for any of the following positions: ASIC RTL Design Engineers Design Verification Engineers Analog Design Engineers Linux Device Driver Engineers Blue-Tooth Engineers Specific experience requirements include: - RISC-V processor experience, 4+ years, in Bangalore - Design Verification with PCIE, 5+ years, in Bangalore - DFT with Synopsys Tool experience (Tetrax max / Verdi), 4+ years, in Bangalore and Hyderabad - RTL Design Development, synthesis, CDC, LEC, and static timing analysis The positions available are suitable for individuals with 4 to 15 years of experience. Multiple positions a...

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation ...

You are a highly skilled and motivated Senior CAD Engineer responsible for supporting and enhancing the front-end EDA infrastructure. Your expertise in CAD tools, scripting, and ASIC design flows will be instrumental in developing efficient and scalable methodologies for large-scale silicon projects. Your key responsibilities will include deploying and supporting front-end EDA tools such as RTL simulators, static checkers, and formal verification tools. You will be required to develop automation scripts for regression and debug flows, administer and optimize Linux-based compute infrastructure, and collaborate with internal teams to identify CAD needs and deliver tailored solutions. Additiona...

You have an immediate job opening with one of our valuable clients in HYD locations for FPGA with Firmware profiles. The ideal candidate should have a minimum of 8 years of experience in FPGA, RTL Design, RTL Coding, Firmware, CDC, and Lint. The location for this position is in HYD with a notice period of immediate to 15 days. If you are interested in this opportunity, kindly share your updated profile with Anand Arumugam at anand.arumugam@modernchipsolutions.com or call at +919900927620 for further discussion.,

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulation...

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically the Hardware Engineering team. In this role, you will be responsible for developing micro-architecture and RTL design for security-related Cores, focusing on block level design. Your tasks will include enabling software teams to utilize hardware blocks efficiently and running ASIC development tools such as Lint and CDC. It will be crucial for you to report progress and communicate effectively against set expectations. As a qualified candidate, you should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, with a minimum of 5 years o...

As a Senior Silicon Design Engineer at AMD, you will play a key role in contributing to the development and verification of cutting-edge technologies that drive innovation in the computing industry. Your passion for modern processor architecture, digital design, and verification will be instrumental in ensuring the highest quality products are delivered to the market. In this role, you will collaborate with a diverse team of engineers to implement front-end designs from RTL to netlist, conduct formal verification checks, and debug any timing, area, or congestion issues that may arise. Your ability to analyze inter-block timing and develop timing constraints will be crucial in optimizing the ...

As an Electrical Senior Principal Engineer in our Electrical Engineering team in Bangalore, you will play a crucial role in the full hardware development lifecycle, from concept to production. Your expertise in system architecture definition, design, analysis, prototyping, sourcing, debugging, and validation of layouts will contribute to delivering state-of-the-art products that cater to the changing world's needs. Collaborating closely with designers, cross-functional teams within Dell Technologies, and suppliers, you will ensure that electronic designs meet various requirements, including schedule, feature set, functionality, quality, and industry standards. Join us in making a significant...

What You'll Do: AWS Services: RDS, DynamoDB, Aurora, DMS (Database Migration Service), EC2, S3, VPC, CloudFormation, CloudWatch, IAM AWS Database Solutions: Hands-on with SQL (PostgreSQL) and NoSQL databases (DynamoDB) on AWS . Cloud Security: Encryption, IAM policies, security groups, data masking, KMS High Availability & Scalability: Multi-AZ deployments, read replicas, auto-scaling Backup & Recovery: Point-in-time recovery (PITR), snapshots, backups Database Migration Tools: AWS DMS, SCT, native database tools (e.g.pg_dump) Downtime Minimization: CDC (Change Data Capture), blue-green deployments, replication Expertise You'll Bring: 5+ years of experience in AWS and Dynamo DB Proficiency i...

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified...