ASIC/RTL Design Engineer(Camera) - Sr Lead Qualcomm

8.0 - 15.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: 8-15 years of relevant ASIC design experience Solid experience in digital front end design for ASICs Exper...

Posted 1 week ago

AI Match Score

Apply

Principal Engineer, ASIC Development Engineering Western Digital

7.0 - 11.0 years

0 Lacs

karnataka

On-site

Role Overview: You will be responsible for designing ASIC/IP Digital Design for large SOCs, utilizing your expertise in Verilog/SV implementation for complex designs with multiple clock domains. Your role will also involve working on various bus matrices like AHB, AXI, and NOC designs, and experience with ARM processor and/or NAND Flash subsystems would be advantageous. Additionally, you will contribute to low power design methodology, clock domain crossing designs, Spyglass Lint/CDC checks, report analysis, and signoff. Proficiency in Perl, Python, TCL language, and the ability to collaborate effectively with Verification/Validation teams are essential. Your positive attitude, problem-solvi...

Posted 1 month ago

AI Match Score

Apply

ASIC RTL Design Engineer - Qualcomm

2.0 - 6.0 years

0 Lacs

hyderabad, telangana

On-site

Qualcomm India Private Limited is seeking a talented individual to join their Hardware Engineering team. As a part of the Engineering Group, you will be responsible for ASIC design with a focus on digital front end design. The ideal candidate should hold a PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with 3-5 years of relevant experience in ASIC design. Key responsibilities include RTL coding in Verilog/VHDL/SV for complex designs with multiple clock domains, expertise in bus protocols like AHB, AXI, and NOC designs, and experience in low power design methodology and clock domain crossing designs. Additionally, the candidate should have ...

Posted 5 months ago

AI Match Score

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.