69 Calibre Jobs - Page 3

As a Senior Physical Design Engineer, you will be responsible for leading the Netlist-to-GDSII implementation process on advanced submicron technology nodes. Your expertise in utilizing industry-standard EDA tools and your understanding of timing closure and physical verification will be crucial for this role. Your key responsibilities will include driving the entire Netlist-to-GDSII flow, which involves tasks such as floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. You will also be required to conduct Static Timing Analysis (STA) to ensure timing closure across all design corners, as well as execute power integrity and physical verification checks (LVS, DRC). Col...

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for ...

5+y in Physical design verification,Power analysis Tcl,AWK,python scripting Calibre,Innovus,Voltus layout edits in Innovus,power reports(IR, EM) from Voltus DRC report from Calibre fixing in Innovus IR,EM reports from Voltus fixing in Innovus

You will be responsible for executing customer projects independently with minimum supervision, guiding team members technically in various fields of VLSI Frontend Backend or Analog design. As an individual contributor, you will take ownership of tasks/modules such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc., leading the team to achieve results. Your responsibilities will include completing assigned tasks successfully and on-time within the defined domain(s), anticipating, diagnosing, and resolving problems, coordinating with cross-functional teams as necessary, delivering on-time quality work approved by the projec...

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks...

Primary Skills; Physical Design Methodologies / submicron technology of 28nm and lower Mandatory Skills: VLSI Physical Place and Route Must have: Synopsys/Cadence tools (Innovus, ICC2, Primetime, PT-PX, Calibre) Programming in Tcl/Tk/Perl

As a digital chip designer and customer support specialist, you will collaborate closely with customers to understand their design requirements and provide technical support throughout the implementation phase. Your responsibilities will include identifying, troubleshooting, and resolving design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. You will be hands-on in utilizing relevant EDA tools like Innovus, IC compiler, Calibre, PrimeTime, etc. Additionally, you will assist in the tapeout process, ensuring that all design files are correctly prepared and submitted for manufacturing. To excel in this role, you must hold a Bachelor's or Master's degree in ...

You will collaborate with customers to understand their design requirements and provide technical support throughout the implementation phase. Your responsibilities will include identifying, troubleshooting, and resolving design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. It is essential for you to be hands-on in relevant EDA tools like Innovus, IC compiler, Calibre, PrimeTime etc. Additionally, you will assist in the tapeout process, ensuring all design files are correctly prepared and submitted for manufacturing. To qualify for this role, you should hold a Bachelor's or Master's degree in Electrical Engineering or a related field. You must have prov...

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manag...

Youzentech Technologies is currently seeking an experienced Analog IC Layout Engineer to be a part of our team in Hyderabad. If you possess 5-10 years of expertise in Custom Mixed-Signal Layout Design, we are eager to hear from you. The position is based in Hyderabad/Bangalore and requires the following qualifications and responsibilities: - Proficiency in Full Custom & Semi-Custom Analog IP & IC Layout, starting from schematic to verification - Hands-on experience with various components including Temperature Sensor, SerDes, PLL, ADC, DAC, LDO, Bandgap, Charge Pump, Current Mirrors, Differential Amplifier, and more - Skilled in LVS/DRC debugging & verification for 16FF and below nodes (TSMC...

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including D...

Job Specs : We are seeking a highly skilled and motivated ASIC Physical Design Experts to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Design IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location and Expertise: Bangalore : 4 Years 15 Years Beijing : 8 Years 10 Years Chennai : 3 Years 6 Years Vietnam : 8 Years 10 Years Taiwan : 8 Years 10 Year...

Requirements Good knowledge of Standard cell layout design Good knowledge of CMOS logic Experience in working on Std cell Layout for Bulk CMOS. FINFET experience is not a must but preferable. Expertise in using industry-standard tools like cadence Virtuoso, Calibre Experience in implementation of ESD layouts, handling Antenna/EM, etc Ability to independently debug layout issues Good team player Good in SKILL programming or other scripting languages

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skil...

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Develop or enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from chip level to block level) Active participation in post silicon validation, correlation and test activities using in-house test and validation lab Effectively lead highly energetic and intellectual team members through coaching and mentoring, provide technical direction for career planning, engage them on project issues, and manage change Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Quartz, Calibre, internal tools & flow Perform custom RF Physical Design, including block-level and top level layouts...

We are looking for a skilled EPUB Developer to join our team and work on creating, formatting, and optimizing digital books and e-learning content. The ideal candidate should have experience in EPUB development, knowledge of accessibility standards, and expertise in HTML, CSS, and XML for structured content development. Key Responsibilities: Develop and convert content into EPUB2 and EPUB3 formats, ensuring compatibility across different devices and platforms. Format and structure eBooks using HTML, CSS, and XML to maintain consistency and readability. Implement accessibility standards (WCAG, ARIA, DAISY) to ensure compliance with accessibility guidelines. Optimize and validate EPUB files us...

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Key Skills: Netlist to GDSII flow, CTS, timing closure DRC, LVS, PERC, ERC, Soft Checks Tools: Innovus, ICC, PrimeTime, Calibre, Redhawk Worked on 28nm & below nodes Strong debugging and custom routing skills.