5.0 - 9.0 years

0 Lacs

mysore, karnataka

On-site

Role Overview: As a DV Lead Engineer at TekWissen in Mysore, your responsibilities will include: Key Responsibilities: - Build test plan, tests, coverage assertions from Specification. - Architect and build testbench and testbench components with expertise in UVM, SV, and C SVA. - Demonstrate familiarity with industry protocols like AXI, APB, AHB, PCIe, SoC. - Showcase strong debugging skills and experience with industry standard EDA tools such as Synopsys, Cadence simulators, and debugging tools. Qualifications Required: - Experience with scripting and automation. - Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS...

Posted 1 month ago

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Senior Design Verification Engineer Globex Digital

0.0 years

0 Lacs

hyderabad, telangana, india

On-site

JD Design Verification Understanding the business requirements and functional specifications of the IPs, subsystems and SOC Creating Verification Environment Architecture document Reviewing and Revising: working towards meeting agreed upon acceptance criteria Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification Performing RTL simulations using Synopsys and Cadence simulators Debugging and resolving problems found by simulations .Performance test plan development and maintenance Development of transactors, monitors and models for performance verification. Implement performance verification flow including monitoring, sync...

Posted 1 month ago

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