6 Cadence Modus Jobs

Job Title: DFT Practice Head Location: Bengaluru, India Experience: 12 to 16 years Position Overview The DFT Practice Head will lead the organization's Design for Test (DFT) competency, overseeing strategic direction, technology advancement, and team excellence. This leadership role will be responsible for building and strengthening DFT capabilities to support complex ASIC and SoC programs, ensuring quality, performance, and delivery excellence. Key Responsibilities Define and implement the overall DFT strategy, methodology, and best practices across projects and teams. Lead and mentor a team of DFT engineers, fostering a culture of technical excellence and continuous learning. Drive executi...

Job Description You are required to be an experienced DFT Engineer with a strong background in Scan, ATPG, and MBIST for SoC/ASIC designs. Your main responsibilities will include implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key Responsibilities - Implement and verify Scan, ATPG, and MBIST for complex SoCs. - Perform pattern generation, coverage analysis, and debug. - Integrate and validate MBIST with appropriate memory test algorithms. - Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff. - Develop automation scripts to streamline DFT flows. Qualification Required - Minimum 4 years o...

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1....

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure hi...

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1....

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure hi...