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3.0 - 8.0 years
6 - 8 Lacs
hyderabad, telangana, india
On-site
Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%) Able to characterize basic STD Cells Writing ARC for STD cell char (using primeLib , Silicon smart) lib QA check Circuit understanding block wise , Full chip level Static timing Analysis of DRAM block wise , top level analysis , cell level analysis Writing constraints , analysing the STA reports Reporting violations to Design team , ownership for closure Parasitic modelling and assisting in design validation, reticle experiments and required tape-out revisions Performing verification processes with modelling and simulation using industry standard simulators Contributing to cross group communication t...
Posted 2 months ago
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