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5.0 - 10.0 years
9 - 19 Lacs
Bengaluru
Work from Office
5+ Years of experience (in STA), Timing analysis, validation and debug across multiple PVT conditions using Tempus, Both block level and full chip timing closure at lower nodes 22nm, 16nm, 5nm, tcl, python scripting, ADI flows/ Cadence flows for STA
Posted 4 months ago
4.0 - 10.0 years
0 Lacs
karnataka
On-site
The role requires you to execute small to mid-size customer projects in various fields of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning specific tasks related to RTL Design/Module and providing support to junior engineers in areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. It is crucial to independently analyze and complete assigned tasks within the defined domain successfully and on-time, ensuring on-time quality delivery approved by the project lead/manager. You will be evaluated based on the quality of deliverables, timely delivery, reduction...
Posted 4 months ago
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