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Analog Circuit Design (PLL) Engineer Samsung Semiconductor

5.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Analog Circuit Design Engineer for High-Speed Interface - PLL at Samsung Semiconductor India R&D Center in Bangalore, you will have the opportunity to work on cutting-edge silicon solutions that push the limits of computing. With 5-12 years of relevant experience in Analog and Mixed Signal Design, you will be responsible for designing low jitter and high-frequency PLLs, both LC and Ring-based, as well as General Purpose ADCs, thermal sensors IP, high-speed Serdes, LDOs, BGRs, and other power management blocks. Your role will involve full IP design cycle exposure in advanced Samsung foundry processes of 4nm and below. You will be part of a team that thrives on solving complex digi...

Posted 3 months ago

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