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5.0 - 10.0 years

0 Lacs

pune, maharashtra

On-site

As a Staff Design Engineer at Lattice, you will play a crucial role in designing and developing RTL for a Machine Learning engine. Your primary responsibility will be to efficiently implement ML operators using resources on low power FPGA. To excel in this role, you must have experience in optimizing data paths for high throughput and low latency. A strong understanding of neural network accelerators and/or DSP processors is essential for success in this position. Key Responsibilities: - Design and develop RTL using Verilog, System Verilog-HDL - Conduct functional simulation using industry standard tools - Implement ML operations such as convolution and BatchNorm - Work on image processing a...

Posted 2 days ago

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