Design and Verification Engineer Techno Facts Solutions

3.0 - 8.0 years

10 - 15 Lacs

noida, pune, bengaluru

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Roles and Responsibilities Design verification using UVM methodology for IP/SOC level verification. Create testbenches from scratch, including drivers, monitors, and scoreboard components. Develop VIPs (Virtual Interface Platform) for functional verification of IP blocks. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer review process to ensure high-quality deliverables.

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Design Verification Engineer Ã¢â‚¬â€œ Position 1 Smart Soc Solutions

5.0 - 10.0 years

5 - 8 Lacs

Bengaluru

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Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). Proficiency in PTP 1588 standard and various Ethernet frame types. Competence in packet insertion/extraction techniques. (Additional knowledge of AXI protocol would be considered an advantage) UVM/SV Proficiency Showcase strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Architectural Skills Proven ability to architect, build, and maintain a comprehensive verification stack. Test Development Extensive experience in developing a set of regression tests for verification purposes. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). Excellent understanding of Ethernet protocols, ranging from 100G to 800G. Proficiency in PTP 1588 standard and various Ethernet frame types. Experience with packet insertion/extraction techniques. Knowledge of AXI protocol (preferred). Proven ability to architect, build, and maintain verification stacks. Demonstrated expertise in developing a comprehensive set of regression tests. If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of cutting-edge technology, we encourage you to apply. Join our dynamic team and contribute to the advancement of next-generation technologies. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

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DFD (Design For Debug) DV Smart Soc Solutions

8.0 - 13.0 years

3 - 6 Lacs

Hyderabad

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Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Strong communication skills, both written and verbal Experience: At least 8 years of professional experience in the field Skills: Proficiency in Trace, Cross-Trigger, JTAG, and AXI protocols Expertise in security protocols, real boot processes, Debug mode, Warm reset, power management, and LP-UPF Previous experience with AMD is considered an advantage NoteInterested candidates should submit a detailed resume highlighting their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

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Design and Verification Engineer Coventine Digital

5.0 - 10.0 years

8 - 18 Lacs

Bengaluru

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Job Description: We are looking for a skilled Design Verification (DV) Engineer with strong experience in AXI protocols and Verdi for debugging. The ideal candidate should have hands-on expertise in simulation, debugging, FSDB handling, and coding for verification environments. Key Responsibilities: Work on verification of SoC/IP-level modules using industry-standard protocols (AXI preferred) Run simulations, generate and open FSDBs for waveform analysis Debug RTL and testbench issues using Verdi or similar waveform tools Collaborate with RTL and design teams to ensure functional correctness Develop, execute, and maintain testbenches and testcases for various blocks Must-Have Skills: AXI protocol experience (AMBA bus) Strong Verdi usage for debugging Hands-on experience in running simulations and opening FSDB files Proficient in SystemVerilog and UVM methodology Excellent debugging and problem-solving skills

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