285 Axi Jobs - Page 4

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Digital Verification Engineer for IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create job s, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Digital Verification Engineer for for Mixed-Signals IPs, ASICs and Chipsets used in Qualcomm Snapdragon power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc") and high efficiency power management (DC-DC charge pumps, bucks and linear regulators). * Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches. * Digital Verification aspects include all stages of the verification process from test planning, UVM-compliant test-bench architecture, constrained-random stimulus creation, score-boarding and coverage closure. * Work includes verification of digital and mixed-signals IPs and exposure to analog behavioral models is a plus. * Work includes debugging of complex embedded systems including SOCs, firmware, embedded sequencers. * Position includes IP or chip DV ownership including task planning and project risk mitigation. * Work in a dynamic team environment with aggressive schedule towards metrics-based high quality target. Preferred Qualifications Strong troubleshooting skills across embedded systems disciplines (digital RTL, Firmware, analog behavioral models) Strong communication and organizational skills Strong process-oriented mindset. Expert-level System Verilog Programming Advanced UVM/SV (Universal Verification Methodology using System Verilog) Python or Perl scripting Minimum Qualifications Bachelor's degree in Science, Engineering, or related field. 8+ years ASIC design, verification, or related work experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D (WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies. In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective. The responsibilities will majorly include : Understanding of Wireless systems PHY TX and RX design paths, Algorithms that control the various aspects of wireless systems. Own complete IP/Block/SS level DV. Own end to end DV tasks from design analysis, Verification Plan development , Coding Test bench and test cases, write assertions, running simulations and achieving all coverage goals. Explore innovative DV methodologies (formal, simulation and emulation based) to continuously improve the quality and efficiency of test benches. Successful candidate will be required to collaborate with worldwide design, architecture teams and other stake holder to achieve all project goals. Hence, strong communication skills are a must. Skills/Experience: 2-10 years of strong experience in design verification Strong knowledge of System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology Proven experience of building or maintaining a medium to complex SV/UVM environments Proven experience of writing efficient constraint random tests Prior Experience in verifying WIFI, Modem PHY layer is a strongly desirable. Strong debugging and analytical skills and independent problem-solving ability Proficient in debugging RTL/TB issues using Verdi or similar tools Experience in formal / static verification methodologies will be a plus Good understanding of Wireless protocols, Modem/Wifi Standards is a plus Experience with Power Aware verification, GLS, and scripting languages such as Perl, Python is a plus. Experience in formal / static verification methodologies will be a plus Preferred Qualifications: Understanding of Wireless protocols, Modem/Wifi Standards Experience in IP verification of DSP related HW blocks. Knowledge on scripting languages such as Perl and(or) Python Education Requirements BE/BTech/ME/MTech/MS Communication Engineering and/or Electronics, VLSI , from reputed university preferably with distinction Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview We are looking to hire a strong DV engineer to work on verification of LPDDR/DDR based IPs and Subsystems in the Infra IP team Create DV infrastructure for verification Integrate VIP's Create and execute test plans, debug failures, write assertions, close code and functional coverage Ensure high quality verification Working with all stakeholders to ensure program success Minimum Qualifications Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field. 4+ years Hardware Engineering experience or related work experience. Preferred Qualifications Following skill set is required: Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Preferred Qualifications 4+ Year of industry experiences in the following areas- Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation Get to work on the latest and cutting-edge tech nodes Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure. Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . Candidates should have 5-8 years experience. Good in SV, UVM, Assertions, GLS Solid knowledge of C and Scipting language like python Working knowledge of bus protocol like AHB/AXI Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Responsibilities will include to be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 3-6 years of work experience in ASIC IP cores design RequiredBachelor's, Electrical Engineering PreferredMaster's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred. Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Strong experience in micro architecting RTL design from high level design specification. Excellent problem solving skills, strong communication and team work skills are mandatory. Self-driven, needs to work with minimum supervision. Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus Ability to lead a small design team. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Functional Verification Engineer In the role of GPU Functional Verification Engineer, your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools- working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools- both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation Get to work on the latest and cutting-edge tech nodes Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure. Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience. Should have a working knowledge of bus protocols like AHB/AXI . Candidates should have 5-8 years experience. Good in SV, UVM, Assertions, GLS Solid knowledge of C and Scipting language like python Working knowledge of bus protocol like AHB/AXI Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT is currently seeking digital verification engineers for the mixed-signal ASICs that support QCTs mobile platforms for next generation 5G RFIC/PMIC/Codec technologies. Successful candidates will be working on the following - Block/Subsystem/SoC level digital IP verification using constrained-random coverage methodologies at both RTL and Gate Level. The skills involved includes SV/UVM/UVM_REG/Randomization/Coverage/SVA. Preferred Qualifications -Experience in writing Test Plans independently -Experience with debugging RTL & Gate level simulations -Experience with Functional Coverage &Code Coverage -Experience with Scripting in perl, python, tcl -Experience in planning Verification architecture, review testbench/ testplans with juniors, identify coverage gaps, propose alternate methods for coverage - Should have been involved in leading a chip DV effort - Silicon Debug Experience a plus. - Experience with Mixed Signal Designs involving DSP a plus - Modeling Experience with Matlab, Octave a plus Minimum Qualifications RequiredBachelor's, Electronics or EE PreferredMaster's, VLSI, Electronics or EE. 5+ years ASIC design, verification, or related work experience Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 8+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary 8-15 years of relevant ASIC design experience Solid experience in digital front end design for ASICs Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains Expertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus Expertise in post-Si debug is a plus Good documentation skills Ability to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC Design and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed. Analyze reports/waivers or run various tools Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG

Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead project execution Good to Have: Scripting and automation (Perl/Python/TCL) Experience with UPF simulations , GLS , and Formal Verification Exposure to SoC-level verification Strong communication and leadership abilities

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

Job Title:DEVOPS- AWS Glue, KMS, ALB , ECS and Terraform/TerragruntExperience5-10YearsLocation:Bangalore : DEVOPS, AWS, Glue, KMS, ALB , ECS, Terraform, Terragrunt

As a SoC RTL Design Engineer at Lattice Semiconductor, you will join the HW design team focused on IP design and full chip integration. This exciting position offers the opportunity to be part of a dynamic team where you can contribute, learn, innovate, and grow. Located in Pune, India, this full-time role will concentrate on RTL design, full chip integration, and projects within similar time zones, providing ample opportunities to work on cutting-edge technologies. Your responsibilities will include working on RTL design with best-in-class coding styles, algorithms, and utilizing Verilog and System Verilog. You will also be involved in SoC integration and quality checks such as lint, CDC, RDC, SDC, etc. Collaborating closely with the architect and micro-architect team, you will define design specifications and work towards accelerating design time and improving quality through logic design of key blocks and full chips. To be successful in this role, you should have a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in driving logic design across various silicon projects. Expertise in SoC integration, defining micro-architecture, and experience with 3rd party IP selection is required. Additionally, familiarity with FPGA designs, ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, and debug architecture will be advantageous. You should be an independent worker and leader with strong problem-solving abilities, capable of working with multiple groups across different sites and time zones. Occasional travel may be required as part of the role. Lattice Semiconductor values its employees and offers a comprehensive compensation and benefits program to attract, retain, and reward top talent in the industry. Lattice Semiconductor is a service-driven developer of innovative low-cost, low-power programmable design solutions with a global workforce that is dedicated to customer success and driven to achieve excellence. If you are passionate about working in a fast-paced, results-oriented environment and believe you can thrive in a demanding yet collegial atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice Semiconductor.,

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-12 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash.. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE