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10.0 - 12.0 years

20 - 35 Lacs

Gurugram

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Min 10 yrs of R&D experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. EDA Functional Simulation tools – Synopsys or Mentor or Cadence.

Posted 17 hours ago

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