5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for performing chip-level floorplanning, partitioning, timing budget generation, and power planning. Additionally, you will execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation. Your duties will also involve handling block-level implementation from netlist to GDSII, driving timing closure for high-frequency blocks, and managing blocks with high instance counts (1M+). Moreover, you will ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification, applying signal integrity (SI) prevention and fixing methodologies, and conducting layout edits and physical design optimizations. Furthermore, you will be expected to automate design tasks and manage UNIX-based environments. Your primary skills should include chip-level and block-level physical design expertise, hands-on experience with Synopsys ICC and PrimeTime, proficiency in signoff closure for timing, power, IR, and physical verification, a strong understanding of SI and OCV impacts and mitigation strategies, experience with high-frequency designs and large instance count blocks, and proficiency in layout editing techniques. Your secondary skills should encompass familiarity with Mentor Olympus and Atoptech toolsets, experience in design automation, proficiency in UNIX systems, and scripting knowledge in Tcl and/or PERL. As for educational qualifications, a Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field is required.,

Posted 1 week ago

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