7.0 - 11.0 years

0 Lacs

karnataka

On-site

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic simulators from various vendors is required. Proficiency in ATPG tools like Cadence Modus, RTL lint tools such as Jasper, and scan insertion is highly valued. Candidates with programming skills in Perl, Tcl, Python, or other scripting languages will be preferred. Experience in post-silicon validation, ATE debug, and support is desirable. Familiarity with RTL-to-GDS flow, synthesis, scan insertion, STA, and IR drop tasks is a plus. A good grasp of logic design, RTL implementation, verification, logic synthesis, Logic Equivalent Checking, and Static Timing Analysis is advantageous. As part of the team, you will play a crucial role in developing new DFT methodologies and solutions to enhance quality, reliability, and in-system test and debug capabilities. If you are passionate about making a difference in the technology industry and enjoy tackling complex challenges, we invite you to join us in our mission to solve problems that others cannot.,

Posted 5 days ago

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