3.0 - 7.0 years

0 Lacs

bangalore, karnataka

On-site

As an experienced ASIC/SoC designer with 3-5 years of experience, you will be responsible for the following key responsibilities: - Definition and development of signoff methodology and corresponding implementation solution. - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. - Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. - Streamlining the timing signoff criterions, timing analysis methodologies and flows. - Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Collaborate with Systems and Architecture, So...

Posted 3 weeks ago

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RTL Design - Sr Lead Qualcomm

5.0 - 10.0 years

0 Lacs

karnataka

On-site

As an RTL Design Engineer at Qualcomm India Private Limited, you will be responsible for developing micro-architecture and RTL design for Cores related to security. Your role will involve block level design, enabling software teams to use hardware blocks, and running ASIC development tools including Lint and CDC. You will report status and communicate progress against expectations. **Key Responsibilities:** - Develop micro-architecture and RTL design for Cores related to security - Responsible for block level design - Enable software teams to use hardware blocks effectively - Run ASIC development tools including Lint and CDC - Report status and communicate progress against expectations **Qua...

Posted 1 month ago

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Static Timing Analysis (STA) & Place and Route (PNR) Randstad India

10.0 - 14.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. Your main focus will be on achieving robust timing closure and optimal physical implementation with a keen eye on power, performance, and area optimization. It will be your duty to develop and enhance methodologies for STA and PNR that are specifically tailored to address the unique challenges faced by large, multi-interface, or mixed-signal subsystems. Your role will also involve driving automation and validation of timing and physical design data across subsystem boundaries. Furthermore, you will be required to mentor and provide guidance to junior engineers, nurtur...

Posted 4 months ago

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