561 Asic Jobs - Page 23

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Job Overview TE Connectivity seeks a dynamic and experienced Mixed Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its TE Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support TE Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to TE stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level. Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Willingness to travel as required, 10~25% WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits

About Marvell . Your Team, Your Impact The team is responsible for the post-silicon validation of high-speed transceiver ASICs for coherent optical communications within Marvell s Coherent DSP Business Unit. The team develops software validation platforms, performs post-silicon validation of hardware and firmware components of the ASIC, develops and documents user interfaces for customers, and provides technical support to Marketing, Applications, and customers. What You Can Expect The Marvell Cloud Platform team is looking to hire a QA engineer whose role is to design and execute test plans and test cases that ensure the delivery of high-quality product to customer. Successful candidates must have a strong passion for the latest technologies and strong problem solving and troubleshooting skills. Work closely with peers in a team of skilled engineers designing and developing networking software for Switch Products. Roles and Responsibilities include - Understanding, analyzing and reviewing system requirements, functional specifications, technical design documents. Plan, create and execute test plans based on functional spec documents. Automate and execute test suites with highest quality. Ability to work and co-ordinate with teams across the different verticals. Establish Quality Assurance Engineer strategy and best practices. Stay current with industry trends in testing strategies. What Were Looking For Bachelors/Masters degree in Computer Science, Electrical Engineering or related fields and 6-15 years of related professional experience Ability to create comprehensive test plans and test cases, define testing strategies. Strong understanding of networking concepts and in-depth L2, L3 knowledge. Experience with Python and other object-oriented scripting/programming languages. Experience working with Traffic generators like IXIA and Spirent. Strong communication skills. Experience working on SONiC NOS is an added advantage. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1

Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Experience in performance tuning and debugging system level issues Experience in DPU or AI-NIC development is a huge plus ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: 10 years of experience in software development in domains of networking, RDMA, or system software Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience working in different operating systems or server environments is a plus Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Experience in performance tuning and debugging system level issues Experience in DPU or AI-NIC development is a huge plus ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent

Responsibilities Candidate should have experience in Software development, tools development role, firmware development role or validation tools development. Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical Expertise:Very proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture Knowledge:In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache Coherency:Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and Concepts:Atleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verificationplans,environment, testbenches and writing testcasesto verify Cache structures & protocols in processor. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a qualitydesign Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Required technical and professional expertise 5 + years of experience in Functional Verification of processors or ASICs. 3+years of experience in the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processorCache(L2/L3)Coherency, Memory Hierarchy Verification Minimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Cache Coherency Verification Developed test-plans and test strategies for IP/unit/block level verification of Cache Coherency structures in processor/SoC Good object-oriented programming skills inC++/SV, scripting languages like Python/Perl. Knowledge of functional verification methodologylikeUVM/OVM Knowledge of HDLs (VHDL/Verilog) Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenarios, debugging and triagingfails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios.

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industrys best high-speed communication devices, delivering the highest throughput and lowest latency for todays AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you will be doing: Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions and analog IPs timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What we need to see: B. SC. / M. SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc. ) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! #LI-Hybrid

Calling all innovators and creators! We re hiring RTL Design Engineers for Bangalore to work on complex ASIC designs and integrations. Experience Required: 3-25 Years Key Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)

Seeking a skilled RTL Design Lead/Manager (ASIC) : - 6-20 years experience in VLSI RTL IP/Subsystem design - Expertise in SoC Clock, Power IP/Subsystem, BUS/Subsystem, and more . Profound grasp of Digital design principles, especially AMBA SoC BUS protocols like APB, AXI, and AHB. . Crafting micro-architecture and detailed design docs for SoC Subsystem, focusing on performance, power, and area requirements. . Exceptional debugging skills and extensive experience with DV tools like Verdi, NCSIM. . Preferable experience in SOC Integration at Top Level, Block Level, or Subsystem level. . Collaborating with DV team for verification coverage enhancement and GLS closure with DV, PD, and Modeling team. . Knowledge in CDC, Linting, UPF, DFT, and Multi-Voltage-Rule-Check analysis. . Familiarity with ASIC Synthesis, static timing reports analysis, Formal checking, etc. . Defining constraints, ensuring critical high-speed path timing closure with back end teams. Exposure to quality processes in SoC design and verification is a plus. Thrive in a fast-paced consumer SoC design environment with stringent deadlines and quality benchmarks. CV submission: pathan.khan@wipro.com