ASIC Engineer 3

• Work with internal Design teams and Methodology teams to successfully Lead/implement Physical Designs of multiple blocks of Complex ASICs . The position requires good understanding of the physical design flow from RTL to GDS several chips tapeout experience. The successful candidate should possess in-depth knowledge experience in physical synthesis, design planning, floor planning, place route, static timing analysis and design closure physical verification

Responsibilities

• Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis fixes, Low Power solution development implementation.
• Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools flow, etc
• Work closely with the methodology team to solve the implementation challenges provide inputs to improve the Physical design flow.
• Experienced in design automation.
• Understanding of Timing constraints, SI prevention, Power reduction.
• Must have prior experience with Synopsys/Cadence/Mentor place and route tools.
• Must have completed design in 16nm and or 7nm..
• Proficient in Unix/TCL/Perl.
• Good communication and presentation skills. Requires good interpersonal skills and problem-solving ability.

Minimum Qualifications

• 4+ years experience in ASIC physical design
• Experience with block implementation, extraction, timing and or full-chip designs
• Strong communication skills
• Strong hands-on TCL/Perl development skills

Preferred Qualifications

• Experience as a full-chip floor planning, routing, or timing lead for a large silicon project
• Track record of taping out complex chips on advanced process nodes