Physical Design Engineer, Sr/Lead/Staff Qualcomm

4.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for the physical design aspects of ASICs, including Place and Route (PnR) flow and methodology. Your key responsibilities will include: - Executing complete PD ownership from netlist to GDS2, encompassing HM level PV, LEC, low-power checks, PDN, and STA closure - Implementing Voltage Islands and low power methodologies, flows, and implementation - Debugging Congestion and Clock Tree Synthesis (CTS) issues - Utilizing PnR tools such as Innovus/Fusion compiler and flow - Familiarity with Sign-off methodologies and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)) - Enhancing existing methodologies and flows - Proficiency in scripting languages like TCL, PERL, and PYTHON - Working effectively in a global team environment - Communicating status and issues of owned tasks effectively Qualifications required for this role include: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering experience, or - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years of Hardware Engineering experience, or - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of Hardware Engineering experience - 4-10 years of experience in physical design, including floorplanning, PNR, CTS, and signoff checks If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing accessible support. You may contact disability-accommodations@qualcomm.com for assistance. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to confidentiality and security. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm, and staffing/recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. If you require more information about this role, please reach out to Qualcomm Careers directly.,

Posted 5 days ago

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SMTS ASIC Physical design FCL Lead Advanced Micro Devices (AMD)

12.0 - 17.0 years

14 - 18 Lacs

Bengaluru, Karnataka, India

On-site

THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBLITIES: Handling SOC floorplanning/Partitioning,Die size estimation Experience on abutted and non-abutted designs Handling of Hierarchical designs (Subfcs),Block partitioning, block pin placement,Feedthrough punching, HFN implementation Planning clock Mesh/Tree at SOC/Sub System level Full SOC bump planning includingGPIO Bump Placement, Pad ring generation/GPIO placement,Hard IP bump placement,GPIO and PG RDL routing Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably ASIC designs. Knowledge on bump placement/critical IP placement. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

Posted 1 month ago

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Urgent Opening For Physical Design Sr Engineer / MTS / SMTS Expertiz

2.0 - 7.0 years

3 - 15 Lacs

Bengaluru, Karnataka, India

On-site

We are looking for an experienced Physical Design Engineer responsible for complete physical design and implementation, including floor planning, P&R, timing closure, power and noise analysis, and back-end verification across multiple advanced node projects. Key Responsibilities: Perform chip floor planning, power/clock distribution, P&R, and chip assembly Achieve timing closure and conduct power/noise analysis Manage complete netlist to GDSII flow for ASIC designs Handle synthesis, STA, and physical implementation of hard-macros and/or full-chip designs Collaborate across teams to ensure successful backend design and delivery Utilize low-power design techniques and apply them effectively in backend flow Develop and maintain automation using scripting languages

Posted 1 month ago

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