ASIC Design Verification

As a Design Verification Engineer at our company, you will be responsible for the verification of chip-level designs to ensure they meet architectural and system requirements. Your key responsibilities will include: - Developing test environments and test bench, along with bus protocol checking - Conducting transaction level checking and performance modeling - Utilizing advanced verification languages like VERA, Specman, and System C (desirable) To excel in this role, you should have: - 3-5 years of solid design verification experience - A minimum educational requirement of a BS in EE, with an MS in EE preferred If you are passionate about ensuring the quality and accuracy of chip designs, we encourage you to email your resume to careers@perfectus.com with the Job Code VE in the subject line.,