241 Asic Design Jobs - Page 3

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

As a DFT Technical Lead , you will be responsible for overseeing the DFT implementation and verification activities for complex SoCs/ASICs, collaborating with cross-functional teams and architects. Your role will involve leading teams technically, providing training and mentoring, and interfacing with customers. Under general supervision, you will engage in engineering work, applied research, and the development/design of new integrated chips, including architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging. Roles & Responsibilities: Hands-on expertise in Full Chip SCAN , Compression , MBIST , ATPG , and other DFT-related skills. Over 10 years of experience, with strong hands-on involvement in full chip DFT design , implementation , vector generation/verification , JTAG , boundary scan , and simulation . Proficient with Scan , Compression , ATPG , and simulation tools such as Mentor , Synopsys , or Cadence . Knowledge of Logic BIST is a plus. Proven track record of participation in successful tape-outs of SoC/ASIC chips at 14nm or below, consistently meeting test targets. Strong understanding of front-end SoC/ASIC design and implementation, including Synthesis and Static Timing Analysis (STA) . Experience in developing and automating flows and scripts in Perl/Tcl to enhance DFT methodologies and processes. Excellent problem-solving , debugging , and proactive approach to challenges. Demonstrated leadership in mentoring/training junior teams , managing projects, and taking on technical leadership roles. Strong customer interaction , communication , and teamwork skills.

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) goals. Collaborate with software teams to define hardware/software interfaces, configuration requirements, and verification collaterals. Partner with verification teams on assertion development, test plans, debugging, and coverage closure. Ensure adherence to industry-standard ASIC design methodologies. Drive design quality and functional safety for automotive-grade solutions. Required Skills & Qualifications: Bachelors/Masters/Ph.D. in Electrical/Electronics Engineering. 5–10 years of hands-on experience in RTL design and microarchitecture development. Strong proficiency in Verilog and SystemVerilog. Proven experience in designing IP blocks for video/audio pipelines. Sound understanding of MIPI CSI and DSI protocols. Experience with high-speed, pipelined, and low-power designs. Familiarity with EDA tools and design methodologies (e.g., Synopsys, Cadence). Experience working on designs complying with automotive functional safety (ISO 26262) is a plus. Excellent problem-solving, communication, and team collaboration skills. Note: Only candidates with a notice period of 30 days or less will be considered. Please share or refer profiles that are strictly relevant to the requirements.

Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You'll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively

Description We are seeking a Staff ASIC RTL Digital Design Engineer to join our dynamic team in India. The ideal candidate will have a strong background in ASIC design and will be responsible for developing high-quality RTL designs, participating in verification processes, and collaborating with multiple teams to ensure successful project completion. Responsibilities Design and implement RTL code for ASIC digital circuits. Perform RTL simulations and verification using tools like ModelSim or VCS. Collaborate with verification engineers to ensure design functionality and performance. Participate in design reviews and provide constructive feedback. Work closely with physical design teams to ensure successful handoff and integration of digital designs. Troubleshoot and resolve design issues during the development and testing phases. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 5-10 years of experience in ASIC digital design and RTL coding. Proficient in VHDL/Verilog/SystemVerilog for RTL design. Experience with digital design tools such as Cadence, Synopsys, or Mentor Graphics. Strong understanding of digital logic design principles and methodologies. Familiarity with ASIC design flow, including synthesis, place and route, and timing closure. Ability to work collaboratively in a team environment and communicate effectively with cross-functional teams.

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You'll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python.

What You ll Need: BTech/MTech in Electrical Engineering or related field. Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology. Strong knowledge of deep submicron process technologies and CMOS processes. Familiarity with JEDEC requirements for DDR interfaces and standards. Experience with ASIC design flow and ESD concepts is an advantage.

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns.

12+ years of experience in ASIC design Proficient in Verilog coding, RTL design and complex control path and data path designs Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints Experience in writing Verilog testbench and running simulations.

Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

About The Role We are looking for a skilled CAD Engineer with expertise in Design Compiler (DC) and PrimeTime (PT) and TCL scripting to join our team The successful candidate will be responsible for developing and maintaining ASIC design flows, ensuring efficient and effective design processes. Key Responsibilities Develop and maintain CAD flows for ASIC design using Design Compiler (DC) and PrimeTime (PT). Create and optimize TCL scripts to automate design processes and improve workflow efficiency. Collaborate with design and verification teams to ensure seamless integration of CAD tools and methodologies. Troubleshoot and resolve issues related to CAD tools and design flows. Stay updated with the latest advancements in CAD tools and methodologies to continuously improve design processes. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 4+ Years of relevant expertise in CAD flow development for ASIC design. Proficiency in TCL scripting, particularly with Design Compiler (DC) and PrimeTime (PT). Strong problem-solving skills and the ability to troubleshoot complex design issues. Excellent communication and teamwork skills. Preferred Qualifications Experience with other EDA tools and scripting languages. Knowledge of digital design and verification methodologies. Familiarity with version control systems and collaborative development environments

Role & responsibilities Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/System Verilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment. Preferred Skills : Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O. Prior experience working with large, cross-functional teams and managing design schedules. Experience with software tools for RTL analysis and optimization. Hands-on experience in leading ASIC projects from specification to production.

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Description: Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities: Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications: Master's/Bachelors degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

General Summary: Qualcomm is the global leader in next-generation always-on Display technologies and is dedicated to building a world-class team to drive industry leadership. Join us as an ASIC Systems Architect developing cutting-edge Display subsystems and peripherals. You will define and validate complex multimedia low-power Display architectures that serve diverse markets including mobile, XR, compute, IoT, wearables, and automotive. In this role, you will own the end-to-end ASIC hardware architecture definition, collaborating with cross-functional teams from product, hardware, and software engineering. You will lead architecture validation, optimize power and performance through modeling and simulation, and support the entire product lifecycle from concept to commercialization. Your work will drive innovative architectures, including patentable designs, positioning Qualcomm at the forefront of Display subsystem technology. Key Responsibilities: Lead system architecture definition and validation for advanced multimedia low power Display ASIC subsystems. Collaborate with product, hardware, software, and cross-functional teams to derive detailed subsystem hardware specifications. Develop and execute architecture validation plans; review design and system test results. Optimize architecture for area, power, and performance through system simulation, modeling, and testing. Support development teams to independently execute based on defined specifications. Provide end-to-end support from concept, post-silicon commercialization, to customer engineering documentation. Define and patent novel system architectures to maintain industry leadership. Utilize tools such as MATLAB, SIMULINK, VISIO, and ASIC design toolchains (Synopsys, Cadence, Mentor). Apply programming and scripting skills (HDL, C/C++, SystemC, Python, Perl, TCL) for design, simulation, and automation. Lead and mentor teams, owning deliverables for small to large projects. Produce technical documentation and participate in design reviews and project meetings. Minimum Qualifications: Bachelor's degree in Electronics, Computer Science, Electrical Engineering, or related field with 7+ years ASIC design, verification, or related experience. OR Master's degree with 5+ years ASIC design, verification, or related experience. OR PhD in a relevant field. Strong knowledge of ASIC hardware architecture, low power design techniques, and system-level performance analysis. Experience with digital hardware design and simulation tools (Verilog/VHDL, Synopsys, Cadence, Mentor). Proficiency with system modeling and simulation (MATLAB, SIMULINK) and scripting (Python, Perl, TCL, C/C++). Proven ability to collaborate across teams and drive complex architecture development from concept through commercialization. Excellent problem-solving skills and technical leadership experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are seeking a highly skilled and experienced Sub-System Hardware Architect specializing in ASIC design for AI to join our dynamic team. The ideal candidate will have a strong background in hardware design and architecture, with a focus on AI sub-systems. This role involves defining and leading the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. Desired Skillset: Proven experience in designing and developing ASIC sub-system hardware components for AI applications. Strong knowledge of ASIC design tools and methodologies. Excellent problem-solving and analytical skills. Ability to work effectively in a team environment. Strong communication and interpersonal skills. Expertise in writing detailed hardware specifications and good documentation practices. Knowledge of micro-architecture, RTL coding, and clock controller design. Strong understanding of low power designs and strategies. Excellent written and verbal communication skills. Minimum Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 8 to 12 years of experience in ASIC design and architecture. Principal Duties and Responsibilities: Define sub-system hardware architecture, covering performance, power strategies, etc. Collaborate with cross-functional teams, including Product, Software, SOC, and Hardware Implementation teams, to define hardware requirements and specifications. Develop and implement ASIC hardware architecture strategies for AI. Conduct power assessment and set power targets as part of the architecture work. Conduct studies to improve performance and identify bottlenecks. Write detailed and precise hardware specifications and maintain thorough documentation. Conduct feasibility studies and risk assessments for ASIC designs. Perform detailed analysis and optimization of ASIC hardware performance. Provide technical guidance and mentorship to junior engineers. Stay updated with the latest advancements in ASIC technology and AI applications. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelors degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl). Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

General Summary: Join Qualcomm's world-class Hardware Engineering team, where we push the limits of technology to enable cutting-edge experiences for a smarter, more connected future. We are seeking a Hardware Verification Engineer with experience in SystemVerilog modeling and mixed-signal verification to support design validation for advanced WAN and GPS radio modules used in 5G chipsets. This role involves developing real-number models , functional verification environments , and working with AMS simulation flows to ensure performance and functionality of complex SoC designs involving RF, analog, and digital components. Key Responsibilities: Develop SystemVerilog real-number models (RNM) for analog and RF blocks used in WAN and GPS subsystems. Create and execute functional verification plans for mixed-signal SoC modules. Build UVM/SystemVerilog-based testbenches , write self-checking test cases, and perform regression testing , debugging , functional coverage analysis , and bug tracking . Perform AMS simulations using SPICE-level tools (e.g., Spectre) and digital simulators in co-simulation environments. Work with Cadence toolsets including Virtuoso, SimVision, and NC-Sim for modeling, debugging, and simulation. Collaborate with cross-functional teams including RFIC/Analog Design , Digital Verification , and DFT Engineers to ensure robust SoC verification. Support post-silicon bring-up and validation for taped-out chips. Automate simulation and verification flows using Perl, Python, and Shell scripting . Minimum Qualifications: Bachelor's degree in Electrical Engineering , Computer Engineering , or a related field and 2+ years of ASIC design or verification experience OR Master's degree in a related field and 1+ year of relevant experience OR PhD in a related discipline. Preferred Skills & Experience: Proficiency with SystemVerilog , UVM , and real-number modeling techniques for analog-mixed signal systems. Strong understanding of electrical circuit analysis and analog signal processing. Familiarity with PLL , ADCs , DACs , and serial programming interfaces (e.g., I2C, SPI). Experience working in AMS environments , including SPICE , Spectre , or similar simulators. Knowledge of Verilog-AMS , behavioral analog modeling , and event-driven simulation strategies. Expertise with scripting in Perl , Python , or Shell for automation and toolchain integration. Strong analytical and debugging skills for large-scale SoC environments. Soft Skills: Strong interpersonal and verbal/written communication skills. Proactive problem-solver with the ability to work independently or as part of a collaborative, cross-functional team. Comfortable working in fast-paced development environments with a focus on quality and delivery.