688 Asic Design Jobs - Page 16

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure syst...

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in...

Good understanding of the ASIC flow and digital concepts RTL Designing knowledge with Verilog or System Verilog. Hands on experience in RTL integration Good knowledge and exposure to defining HW interfaces. Worked on Lint, CDC and RDC Good exposure on the RTL integration Strong programming suits various languages such as Verilog, C/C++, Python, Perl with a knack for problem-solving abilities. Experience working with ARM/RISC V processors Excellent written and verbal communication skills Fundamental understanding of Bus or Pin Planning, Block or Chip Level Floor planning, Clock Tree Synthesis, Static Timing Analysis, Knowledge on USB 3.1 or DDR protocol is plus Good knowledge on the verificat...

THE ROLE: As a member of the EPIC server soc team , you will help bring to life cutting-edge designs.?As a member of the Physcial design/soc integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBILITIES: Working on Constraints, Full chip netlist generation, static timing analysis setup and signoff of multi-corner multi-voltage designs. Owning timing execution to meet timing requir...

THE ROLE: The successful candidate will join AMD's Computing and Graphics Performance Verification team. The team's mandate is to analyze AMD's next generation SOC architecture and performance through modeling and RTL simulation. This role will involve working with SOC and IP architects to evaluate and improve performance, and collaborating with design and verification teams to execute performance verification plans. THE PERSON: The ideal candidate has a passion for modern, complex processor architecture, performance, digital design, and verification. The candidate must have excellent communication skills and experience working with teams in different sites and time zones.The candidate must ...

THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. I...

MTS Product Engineer The Product Engineer position is in the Customer Enablement and Success group, located in Hyderabad, Telangana, India, for an experienced application engineer to focus on FPGA & ACAP design methodologies, compilation flows, design closure ease-of-use, tools specification, validation, documentation and key customers support. As a member of a highly seasoned Product Development Engineering team, the successful candidate will work closely with several R&D teams, internal application design teams and tier-1 customers to improve the user experience and productivity and enable the next generation of high performance computing designs across the UltraScale and Versal ACAP devic...

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.Experience requires demonstrated technical expertise in functional verification, test planning, test bench development, stimulus generation, ch...

As a VLSI Mentor / Guest Faculty specializing in Advanced Digital Systems & Low Power Design at Spandsons Horizon Engineering, you play a crucial role in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This contract role, based in Salem, offers a unique opportunity to directly influence the academic and career growth of 60 aspiring engineers. Your key responsibilities include delivering engaging sessions covering topics such as Advanced Digital System Design with Verilog HDL and Low Power VLSI Design. You will also provide hands-on guidance for lab assignments and projects using various tools like Xilinx Vivado, ModelSim, LTspice,...

You will be joining Qualcomm India Private Limited as a Sub-System Hardware Architect specializing in ASIC design for AI within the Engineering Group > Hardware Engineering. Your primary responsibility will be to define and lead the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. You should have proven experience in designing ASIC sub-system hardware components for AI applications, strong knowledge of ASIC design tools and methodologies, and excellent problem-solving skills. Your role will involve collaborating with cross-functional teams to define hardware requirements, developing and im...

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensu...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performan...

As the owner of Ethernovia's India digital hardware team, you will be responsible for all aspects of digital design and digital verification. This position requires both hands-on technical contribution as well as managerial and technical leadership. You will hire and build your own team to plan and execute the design, verification, and validation of advanced automotive communication semiconductors and systems. Key Qualifications: - BS and/or MS in Electrical Engineering, Computer Science, or related field - Minimum 15+ years combined of ASIC design, verification, and leadership experience - Strong understanding of ASIC design and verification fundamentals and industry standard methodologies ...

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture ...

RTL DESIGN LEAD ENGINEER The ideal candidate will be required to work on both IP development and integration into SoCs catering to various markets and tech nodes. The job will involve RTL design, front-end tools flow, and SoC integration/porting-related tasks. Desired Skills and Experience- 8+ years of Experience Engineering experience with exposure to front end ASIC tool flows Should be self-driven and independent in tracking and closing tasks with respective holders. In depth knowledge of AHB and bus infrastructures like matrix and fabrics Good understanding of ARM based SoC Architecture Exposure to ARM Cortex A/M integration or support Good understanding of SoC DV methodology Good experie...

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral mode...

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). The primary focus of this role will be on Ethernet protocol verification, ranging from 100G to 800G standards. Key Responsibilities: Ethernet Protocol Expertise Demonstrate expertise in Ethernet standards, encompassing 100G to 800G. In-depth knowledge of specific standards, including 100GE (cl45, cl49, CL82, CL91, CL119), 200GE, 400GE (cl161, cl116), and 800GE (802.df/800ETA). P...

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with p...

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and ef...

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly experienced Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification, with a strong foundation in SystemVerilog (SV) and Universal Verification Methodology (UVM). In addition to standard verification skills, this role requires expertise in CDP (Compressed Data Pattern), GDP (Generic Data Pattern), and DFT DV (Design for Test in Design Verification) methods, including JTAG, MBIST (Memory Built-In Self-Test), SCAN, PG (Pattern Generator), and PM (Pattern Memory). Key Responsibilities: IP and SOC Verification Perform comprehensive IP and...

Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate should have a proven track record of worki...

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilities: Understand the overall ASIC f...

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a ...