Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Retail Sales Associate Ambit Semiconductors

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: Are you ready for a challenging career that also brings a sense of accomplishment At Ambit, you will find the perfect platform to excel and advance in the field of semiconductor design. Enjoy the freedom to work in your unique way while receiving the necessary support to learn and enhance your skills. Ambit believes in fostering innovation by empowering its employees to experiment and create. The vibrant work environment reflects the management's dedication to its people and their values. Join Ambit today for a promising future in semiconductor design services. Key Responsibilities: - Develop micro-architecture at IP/sub-system level and perform RTL coding. - Create timing con...

Posted 1 week ago

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ASIC Design Engineer Ambit Semiconductors

5.0 - 10.0 years

0 Lacs

hyderabad, telangana

On-site

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints. - Integrate IP/sub-system. - Perform basic verification either in IP Verification environment or FPGA. - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip, create micro-architecture d...

Posted 1 week ago

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Retail Sales Associate Ambit Semiconductors

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture dia...

Posted 3 months ago

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