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5.0 - 9.0 years
0 Lacs
hyderabad, telangana
On-site
In this role at Ambit, you will be responsible for IP / sub-system level micro-architecture development and RTL coding. Your key responsibilities will include: - Prepare block/sub-system level timing constraints - Integrate IP/sub-system - Perform basic verification either in IP Verification environment or FPGA - Deep knowledge of mixed signal concepts - Deep knowledge of RTL design fundamentals - Deep knowledge of Verilog and System-Verilog - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Power intent, Static Timing Analysis (STA) - Write design specifications for different functional blocks on a chip - Create micro-architecture diagrams of functional blocks - Design functional blocks using System Verilog RTL code - Conduct Synthesis and place and route to meet timing / area goals - Contribute to Design Verification, Synthesis, Power Reduction, Timing Convergence & Floorplan efforts - Code Verilog RTL for high performance designs - Specify, design, and synthesize RTL blocks - Optimize and floorplan them Qualifications required for this position at Ambit include: - B.Tech / M.Tech or equivalent from a reputed University - 5-7 years of relevant experience Join Ambit today for a fulfilling career in semiconductor design services.,
Posted 19 hours ago
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