RTL Design and Signoff, Principal Engineer Synopsys Inc

12.0 - 14.0 years

0 Lacs

noida, uttar pradesh, india

On-site

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise ...

Posted 3 weeks ago

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RTL Design and Signoff, Principal Engineer Synopsys Inc

12.0 - 14.0 years

0 Lacs

noida, uttar pradesh, india

On-site

Posted 1 month ago

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Sr Principal Layout Engg onsemi

10.0 - 14.0 years

0 Lacs

karnataka

On-site

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping o...

Posted 1 month ago

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Analog Layout Engineer Capgemini

0.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Description : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimiza...

Posted 1 month ago

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