10.0 - 14.0 years

0 Lacs

karnataka

On-site

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping out high-performance microcontroller chips and collaborate with cross-functional teams including Chip team, Tech, and CAD. Developing scripts and methods for layout design automation will also be a part of your duties. Onsemi is dedicated to driving disruptive innovations in automotive and industrial markets to create a better future. The company focuses on megatrends like vehicle electrification, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a unique product portfolio, Onsemi develops intelligent power and sensing technologies to address complex global challenges and lead the way in building a safer, cleaner, and smarter world. Minimum qualifications for this role include a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience. Preferred candidates should have experience in analog/mixed-signal layout design of deep submicron CMOS and BCD technologies. Proficiency in interpreting CALIBRE DRC, ERC, LVS reports, programming skills in SKILL, Perl, and/or Python, and experience with CADENCE or MENTOR GRAPHICS layout tools are desirable. Strong understanding of semiconductor manufacturing process, DFM techniques, and familiarity with Cadence Design Environment (CDE) and Unix OS are also required. Effective communication skills and a collaborative team spirit are essential for success in this role.,

Posted 4 days ago

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Analog Layout Engineer Capgemini

0.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Description : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor's or Master's Degree.

Posted 1 week ago

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