78 Apb Jobs - Page 2

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Principal Duties and Responsibilities: 12+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

Overview Job Title: Senior DevOps Engineer Location: Bangalore / Hyderabad / Chennai / Coimbatore Position: Full-time Department: Annalect Engineering Position Overview Annalect is currently seeking a Senior DevOps Engineer to join our technology team remotely, We are passionate about building distributed back-end systems in a modular and reusable way. We're looking for people who have a shared passion for data and desire to build cool, maintainable and high-quality applications to use this data. In this role you will participate in shaping our technical architecture, design and development of software products, collaborate with back-end developers from other tracks, as well as research and evaluation of new technical solutions. Responsibilities Key Responsibilities: Build and maintain cloud infrastructure through terraform IaC. Cloud networking and orchestration with AWS (EKS, ECS, VPC, S3, ALB, NLB). Improve and automate processes and procedures. Constructing CI/CD pipelines. Monitoring and handling incident response of the infrastructure, platforms, and core engineering services. Troubleshooting infrastructure, network, and application issues. Help identify and troubleshoot problems within environment. Qualifications Required Skills 5 + years of DevOps experience 5 + years of hands-on experience in administering cloud technologies on AWS, especially with IAM, VPC, Lambda, EKS, EC2, S3, ECS, CloudFront, ALB, API Gateway, RDS, Codebuild, SSM, Secret Manager, Lambda, API Gateway etc. Experience with microservices, containers (Docker), container orchestration (Kubernetes). Demonstrable experience of using Terraform to provision and configure infrastructure. Scripting ability - PowerShell, Python, Bash etc. Comfortable working with Linux/Unix based operating systems (Ubuntu preferred) Familiarity with software development, CICD and DevOps tools (Bitbucket, Jenkins, GitLab, Codebuild, Codepipeline) Knowledge of writing Infrastructure as Code (laC) using Terraform. Experience with microservices, containers (Docker), container orchestration (Kubernetes), serverless computing (AWS Lambda) and distributed/scalable systems. Possesses a problem-solving attitude. Creative, self-motivated, a quick study, and willing to develop new skills. Additional Skills Familiarity with working with data and databases (SQL, MySQL, PostgreSQL, Amazon Aurora, Redis, Amazon Redshift, Google BigQuery). Knowledge of Database administration. Experience with continuous deployment/continuous delivery (Jenkins, Bamboo). AWS/GCP/Azure Certification is a plus. Experience in python coding is welcome. Passion for data-driven software. All of our tools are built on top of data and require work with data. Knowledge of laaS/PaaS architecture with good understanding of Infrastructure and Web Application security Experience with logging/monitoring (CloudWatch, Datadog, Loggly, ELK). Passion for writing good documentation and creating architecture diagrams.

Experience: 6+ years of experience in pre-silicon RTL Verification /IP Verification / SOC verification, Strong knowledge of System Verilog and working knowledge of recent verification methodologie Required Candidate profile Notice Period: 0- 60 days Education: BE/ B.Tech/ Master degree in Electrical Engineering or Computer Science

Primary Skills Minimum 4+ years of AWS Platform Support experience. Hands-on experience specifically with AWS ServicesECS, CloudFormation, EC2, IAM, S3, ASG, ALB, Route53, SNS, SQS. Minimum 3+ years of Python Development experience (writing unit tests, features, deploying to AWS Lambda, etc.). Minimum 2+ years of DevOps CI/CD Support experience. Experience in handling Non-Prod & Production Releases, following Release & Change management principles. Experience with applying OS/Platform-related Patches, Upgrades, determining Impacts, and Documenting Implementation steps. Good to have experience in DevOps tools (GitHub, Bamboo, Bitbucket, Git), Core Java, Spring Boot, JavaScript, Ansible, Terraform. Exposure to Agile or Scrum methodology. Ability to demo Jira stories to clients, articulate the implementation, explain issues/impacts, and document release notes. Must-Have Skills : AWS ECS and EKS. CloudFormation. Python. Secondary Skills Good to have experience in DevOps tools (GitHub, Bamboo, Bitbucket, Git), Core Java, Spring Boot, JavaScript, Ansible, Terraform. Exposure to Agile or Scrum methodology. Ability to demo Jira stories to clients, articulate the implementation, explain issues/impacts, and document release notes.

SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu or Haps) Understanding of JTAG based debuggers Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Knowledge on verification plans based on design specifications and requirements Proficiency in UVM and SystemVerilog for developing verification environments Unterstanding of protocols like PCIe, USB, Ethernet, or AMBA (AXI, AHB, APB) Required Candidate profile Hands-on experience with debugging tools like Verdi, DVE, or SignalTap Ability to analyze and resolve complex design and verification issues Proficiency in scripting languages like Python, Perl, Shell

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during micro architects development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.This posting is for a position on the DMR IMH OOB Validation Team. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience with validation in both simulation and emulation environments. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

**Verification Planning and Execution*: 2. Develop and execute comprehensive verification plans. 3. Close verification with coverage closure, ensuring high-quality results. 4. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions. 5. **Testbench Development*: 6. Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. 7. Implement reusable Verification IP (VIP) components. 8. Collaborate with third-party VIP providers. 9. Developing vertically and horizontally re-usable test-benches 10. **Methodology and Flows*: 11. Demonstrate a solid understanding of ASIC design and verification methodologies. 12. Apply object-oriented programming principles effectively. 13. Implement constraint random verification methodology. 14. **Technical Skills*: 15. Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI, SV/DPI) 16. Familiarity with industry standards (e.g., I2C/SPI/AHB). 17. Gate level simulation 18. Experience with low-power verification using UPF (Unified Power Format) is a plus. 19. Knowledge of formal verification techniques is advantageous. 20. **Collaboration and Communication*: 21. Work effectively with internal teams and external customers. 22. Strong written and verbal communication skills. 23. Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

What we’re looking for The Infrastructure team is looking for a Software Engineer with deep experience in and passion for cloud systems and software security. Our team works with teams across the company to help ensure that SurveyMonkey’s cloud infrastructure and security standards and practices are world-class. You’ll have the opportunity to develop infrastructure tools, and help teams implement them. What you’ll be working on Maintain and operate AWS environments with well established best practices Partnering with teams across the company include Application Engineering, Security Operations, and Product to provide the technical foundations of our cloud infrastructure and security systems Analyzing our existing systems, and designing and implementing tools to maintain internal security guardrails Providing both technical guidance and mentorship to developers in adopting good security practices in their feature development Developing tools to help SurveyMonkey comply with privacy regulations across the globe We’d love to hear from people with 8+ years of experience with application development 4+ years of experience with AWS, including but not limited to heavy experience with IAM, ALB, S3, AWS Lambda, CloudWatch, Transit Gateway, VPC, CloudFront, Route 53, Cloud Map, and VPN Proficient in AWS security technologies including GuardDuty, ACM, Shield, WAF, and Firewall Manager Demonstrable experience leveraging Configuration Management tooling such as Terraform, and proven strategies for maintaining large infrastructure-as-code deployments A strong understanding of web application security risks and control (e.g., OWASP Top 10) Proficient in Python or equivalent; NodeJS experience a plus Familiarity with privacy regulations like GDPR, CCPA, etc is a plus This opportunity is hybrid and requires you to work from the SurveyMonkey office in Bengaluru 3 days per week. #LI-HYBRID

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : Spring Boot Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : BE Summary :As an Application Developer, you will be responsible for designing, building, and configuring applications to meet business process and application requirements using Spring Boot. Your typical day will involve working with Java, developing and testing applications, and collaborating with cross-functional teams to deliver high-quality solutions. Roles & Responsibilities: Design, develop, and test applications using Spring Boot, ensuring adherence to coding standards and best practices. Collaborate with cross-functional teams to identify and prioritize application requirements, ensuring timely delivery of high-quality solutions. Troubleshoot and debug applications, identifying and resolving technical issues to ensure optimal performance and functionality. Maintain and update existing applications, ensuring compatibility with new technologies and platforms. Stay updated with the latest advancements in Spring Boot and related technologies, integrating innovative approaches for sustained competitive advantage. Professional & Technical Skills: Must To Have Skills:Strong proficiency in Spring Boot. Experienced production support resource who is well versed with incident, problem, change and request management. AWS Cloud based web frontend application; java based microservices/APIs support experience Flexible to work afterhours and weekends on standby roster and support high priority incidents when required Working knowledge of Service Management tools such as ServiceNow, Remedy Monitoring & logging - preferably Cloud watch, Splunk and AppDynamics PostgreSQL Document (JSON) based Database Query and Update Skills Working knowledge of AWS Services Like ECS Cluster, ALB, ASG, ECS, EFS, S3, CloudWatch, Cloud Trail, Dynamo DB etc. Basic Working knowledge of Docker, Kubernetes or other Containers Working knowledge of Jenkins jobs for CI CD Pipelines General SSL certificates knowledge and java key stores Well versed with compliance activities for cloud-based applications such as Disaster Recovery, Application and Database Backup and and Restore, Capacity Management Plans Experienced in supporting projects for go-live implementation, deployments, operational readiness activities (handover, change management, documentation review, release management) Basics of Linux, Bash scripting etc. Working knowledge of REST APIs and Postman RoolAdditional Information: The candidate should have a minimum of 5 years of experience in Spring Boot. The ideal candidate will possess a strong educational background in computer science or a related field, along with a proven track record of delivering impactful solutions. This position is based at our Chennai office. Qualification BE

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Project Role :Application Support Engineer Project Role Description :Act as software detectives, provide a dynamic service identifying and solving issues within multiple components of critical business systems. Must have skills :Cloud Infrastructure Good to have skills :AWS Architecture, AWS Administration Minimum 3 year(s) of experience is required Educational Qualification :15 years full time education Skill – AWS ArchitectureRole:AWS ArchitectureRole Description:Manage the cloud infrastructure environment through cross technology administration (Databases, virtual networks, Security, Monitoring and Backup), Development and execution of script and automations. Manage the environment incidents with a focus on service restoration. Act as operations support for all AWS hosted Virtual Machines, PaaS services, network, storage and security. Design, build and configure AWS Services to meet business process and application requirements.Job Requirements:Minimum 5 years of experience in AWS PaaS services.Key Responsibilities:-Provide L2/L3 support on AWS PaaS service to end-user issues/requests raised in ITSM tools.-Work closely with the architect and engineers to design networks, systems, and storage environment that effectively reflect business needs, security requirements, and service level requirements.-Manage a continuous integration/continuous deployment methodology for the server-based technologies.-Database administration, Performance tuning and storage optimization.-Licensing knowledge and good understanding of patch and package management. -Design, build and configure AWS Services to meet business process and application requirements. -Execution and documentation of infrastructure changes and preparing work instructions.-Incident and Change management, Health and performance Monitoring - Check server health, performance and capacity alerts, take preventive and remedial action.-Reporting and participating in governance and audit activities.-Infrastructure-as-Code for automation of infra and app provisioning and deployment.-Maintaining access control, as well as the integrity of data, throughout the platform of the AWS application-Make necessary improvements in resources and also work on resource tagging to designate plans and costs for governance, reporting, and budgeting-Build and manage Bastion Hosts, C2S access points, and VPC-Efficiently monitor the development and billing of several strategies for cost optimization-Some of the other significant roles of these professionals include:-Managing the complete AWS life cycle, along with security, provisioning, and automation-Administrating and establishing the architecture of multi-tier systems-Fine-tuning and configuring various cloud infrastructures-Performing services such as kernel patching, errata patching, and software upgrades-Creating backups and managing disaster recovery-Effectively monitoring performance degree and its availability-Containerization in a micro services context-Licensing knowledge and good understanding of patch and package management. Technical Experience:-Experience in AWS DevOps, Deploy, manage, and operate scalable, highly available, and fault-tolerant systems on AWS using Jenkins, Github, Ansible, Teraform, Chef, Puppet. -Hands on experience in Docker, Container and Kubernetes -Hands on experience on EC2, EBS, NSG, VPC, S3, ASG, ELB, Route53, CloudWatch, CloudFormation. -Hands on experience on PaaS services - S3, API Gateway, Athena, AWS Backup, AWS Config, CloudFront, CloudTrail, Code Build, Direct Connect, EFS, EKS, EKS, Elastic Cache, ECS, Elastic Search, ELB/ALB, Fargate, FSX, Glue, Key Managed Service(KMS), Kinesis Analytics, Kinesis Firehose, Kinesis Streams, Lambda, Redshift, Route 53, SES, Shield, SQS, Storage Gateway, VPC, WAF, AppStream, Cognito, DataSync, SageMaker, Secrets, AWS Transfer etc.-Hands on experience in Bash Scripting, Terraform, Python. -Reduce the production time necessary via AWS CloudFormation skills to deploy the infrastructure for automation.-Implement and control the flow of data to and from AWS. Migrate on-premises workloads to AWS -Agile delivery mode (e. g. scrum)-System Administration and monitoring-Performance tuning and storage optimization.-Experience in operating system level troubleshooting, resolving system boot issues, Kernel bugs and server log analysis. -Experience in regular operating system Patching and vulnerability remediations. -Experience in Linux System hardening and Non-Compliance remediation. -Learn the metrics and also monitor the overall usage of several AWS resources with the help of Amazon CloudWatch-Knowledge on Ticketing tools preferably Service Now. Professional Attributes:Good analytical and troubleshooting skills with the ability to think logically through a problem. Must have the initiative, tenacity and commitment to see problems through to resolution, Ability to work in shift patterns and provide out of hours On-Call support. collaborate with other team members to develop automation strategies and deployment processes.Education Qualification:GraduateMandatory Certification:AWSOptional CertificationITIL, Linux, Virtualization, Networking, Azure, Microsoft or any other Qualifications 15 years full time education

About The Role Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 2+ years' experience on AMBA protocols. Strong background and experience on Coherent Protocols (IDI, CHI). Strong coding experience in perl, python (one of the programming languages). Strong in coherency architecture. Preferred Qualifications: Bringing up coherent protocols from 0 to1. 2 + years of Experience on Network on Chip verification. 2+ years of experience developing protocol checkers, bridge checkers, VIP integration, Configurable IP verification. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification.Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Java Developer + Cloud Experience Experience in SQL/PLSQL in any database Technologies like Sybase, DB2, DynamoDB. Implemented Docker-Microservices, RESTful API Architecture. Good understanding of Core AWS Services including AWS EC2, S3, ALB, NATGW, EFS, Lambda, APIGW. Ability to create AWS Infrastructure Design including DR at AWS Infra Level. Knowledge in Infra Provisioning using Terraform in AWS. JD Link :

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 6-9 years of experience in SoC design Educational Requirements:6+ years of experience with a Bachelor"™s/ Master"™s degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The role generally entails a mixture of: Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas:- Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience