4 Analog Verification Jobs

Key Responsibilities: Lead verification of analog and mixed-signal IP blocks including: Bandgaps, LDOs, Buck (multi-phase) switching regulators Comparators and Functional Safety (FuSa) monitoring circuits Own and execute block-level verification plans with comprehensive coverage. Develop and maintain analog behavioral models using SystemVerilog Real Number Modeling (SV-RNM) . Verify embedded digital functionalities such as: CRC, Clock Monitoring, OTPs, Register Maps Communication Interfaces (e.g., SPI, IC) Write and implement SystemVerilog assertions and covergroups . Perform advanced debug at both RTL and schematic levels. Manage VSIF files and support regression execution. Perform coverage analysis using tools like IMC or vManager . (Bonus) Scripting using Makefiles or automation tools.

Company Overview Connectpro operates in the human-resources industry, specializing in recruitment and talent acquisition. Role And Responsibilities As a senior analog design engineer at Connectpro, you will be responsible for taking a subsystem of analog design through all phases of the design process. This includes: Creating the architecture of the analog subsystem Providing technical leadership to the team during execution Designing, simulating, and supervising the layout and verification processes Evaluating and debugging silicon samples You will be working with the latest Cadence analogue design tools including Virtuoso Composer, Verilog, HSPICE, and other PC-based tools like Matlab. The circuits you will be working on involve mixed signal blocks such as switched capacitor amplifiers, PLL, RAM, high-speed interfaces, references, IO circuits, data converters, and digital building blocks. Your role will also involve ensuring timely execution and collaborating with cross-functional teams like PE/TE. Experience with custom layout and analog verification is a plus. Candidate Qualifications To be successful in this role, you should possess the following qualifications: Bachelor's degree with 5-8 years of experience in CMOS, analog/power/mixed-mode IC design using tools similar to the ones mentioned above Strong fundamentals in CMOS analog design Excellent communication skills Ability to interact effectively with cross-functional teams Understanding of the semiconductor development flow Skills: hspice,semiconductor development flow,adc,,pll,icdesign,data converters,analog,layout/verification,dac,mixed signal,team management,cadence analogue design tools,custom layout,analog/power/mixed-mode ic design,simulation,evaluation/debug,amplifiers and filters,matlab,interact with cross functional teams,switched capacitor amplifiers,pmic,cmos process,cmos,,ram,ams,virtuoso composer,architecting,design,dll,,digital building blocks,references,analog verification,cmos,io circuits,hispeed interfaces,communication skills,verilog,analog design,

Lead/Senior Analog Mixed-Signal (AMS) Engineers Layout / Verification / Design Locations: Noida | Bangalore | Hyderabad Experience: 7-12 Years Domain: Semiconductor | Analog Mixed-Signal | Custom IP & SoC Design Role Overview: We are hiring skilled and experienced professionals across AMS Layout , AMS Design , and AMS Verification disciplines to join our high-performance analog design team. You will contribute to the development of high-precision, low-power analog and mixed-signal IPs and subsystems targeted at next-generation SoCs in automotive, networking, and consumer electronics domains. Open Positions: Position #1: AMS Layout Engineer Responsibilities: Perform custom layout design of analog and mixed-signal circuits (e.g., ADCs, PLLs, LDOs, Bandgap, Bias, SerDes). Ensure layout quality, LVS/DRC clean , and meet area/power/performance targets. Work closely with circuit designers for floorplanning and layout optimization. Experience in FinFET nodes (e.g., 7nm/5nm) is a strong plus. Tools & Skills: Cadence Virtuoso (Layout XL), Calibre (LVS/DRC), PVS, Assura Strong grasp of matching, isolation, shielding, and analog layout best practices Position #2: AMS Design Engineer Responsibilities: Design and implement key analog/mixed-signal blocks such as amplifiers, voltage regulators, PLLs, SERDES, data converters, and ESD protection. Drive top-down design , simulation, and verification from spec to tape-out. Perform circuit simulation, characterization, and corner analysis . Tools & Skills: Cadence Spectre, Eldo, HSPICE, MATLAB, ADE-XL Good understanding of noise, mismatch, stability, and PVT simulations Position #3: AMS Verification Engineer Responsibilities: Develop AMS simulation environments integrating digital RTL and analog behavioral models. Use mixed-signal verification methodologies to validate complex AMS SoC subsystems. Support behavioral modeling (Verilog-A/AMS) and co-simulation using tools like Xcelium or AMS Designer. Tools & Skills: Verilog-AMS, SystemVerilog, UVM-MS, Cadence AMS Designer, Spectre AMS, Xcelium Knowledge of DFT hooks in analog blocks , test modes, and power intent is a plus Interested? Apply or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Mirafra Technologies is hiring!! Experience Required: 4 to 12 years Location: Bangalore Application Email: swarnamanjari@mirafra.com Job Description • Top-level AMS IC verification using Verilog AMS methodology • Analog modeling using VerilogAMS, SystemVerilog (create new models and update functionality of existing models) • Create verification test specifications • Develop and execute top-level test cases, self-checking test benches and regressions suites • Update the verification environment (update verification components, drivers, checkers, scripts and Tcl procedures to his/her test needs) • Documentation of the work done and verification progress reporting • Written and verbal communication Job Qualification: • Masters or Bachelors in electronic engineering or equivalent • 8+ years of experience in SoC/IP level verification using AMS verification methodology • Must: Decent knowledge of Verilog AMS, System Verilog, Real number modelling, Verilog and/or VHDL design languages; systemC knowledge is a strong plus. • Good UVM understanding and test case building • Analog blocks design specification understanding • Analog/RF design understanding • Knowledge on Model Vs Schematic verification flow • Vmanager regression setup creation and implementation • Experience with Cadence design environment • Experience in programming C, Tcl and Perl Able to identify and resolve complex issues, can work independently