3 Analog Modeling Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. E view modeling Characterization Verilog behavior modeling, timing lib modeling, Power view modeling, model verification of mixed signal analog IPs like DDR-MSIP, DDRIOs,. SERDES analog, ADC/DAC, PLLs e.t.c. . Functional understanding of mixed signal analog IPs as above for modeling and Characterization verification Proficiency in Verilog modeling and verification. Write behavioral Verilog/Verilog MS/real models of analog blocks. Developing and maintaining the self-checking Test-benches /Test-Plans. SV modeling and testbench development for verification against transistor level netlist Proficiency in Simulators such as VCS e.t.c. 5+ years of experience with characterization tool and simulators like Silicon Smart, Hspice, Finesim, Nanosim and Liberty format description Basic skills on AMS verification and knowledge preferable Self-motivation, teamwork, and strong communication skills. Tcl/Perl/Skill Scripting aware for automation You may e-mail or call Qualcomm's toll-free number found . To all Staffing and Recruiting Agencies :

We're looking for a highly experienced and influential Senior Mixed-Signal Design Verification Engineer to join our dynamic team. As a key member of our design verification group, which includes both mixed-signal and digital verification engineers, you'll be responsible for formulating comprehensive verification strategies and leading, driving, and completing the verification of large, integrated products. As a senior contributor, you'll be expected to lead and influence verification methodologies within both your business unit and across Analog Devices. We also encourage active participation in cross-company technical initiatives, as well as patenting and publishing your work when possible. Requirements: B.Tech / M.Tech with 5+ years of industry experience in analog/mixed-signal behavioral modeling at various levels of abstraction, and full-chip verification (AMS and DMS DV). Strong understanding of analog design concepts and mixed-signal design architectures. Exposure to products that integrate a wide variety of analog functions.

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim. Create Liberty (.lib) timing and power models and validate them against transistor-level designs. Develop and maintain self-checking testbenches and test plans for model verification. Conduct functional analysis and verification of modeled IPs using simulators like VCS. Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices. Automate model generation and verification workflows using Tcl, Perl, or Skill scripting. Interface with design and verification teams to ensure model accuracy and completeness. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field and 3+ years of relevant hardware modeling experience OR Master's degree and 2+ years of experience OR PhD and 1+ year of experience. Required Skills & Experience: 5+ years of experience with timing/power characterization and view generation tools (e.g., Silicon Smart, HSPICE, FineSim). Strong understanding of mixed-signal analog IP design and functionality. Expertise in Verilog and Verilog-AMS behavioral modeling. Hands-on experience with simulation and verification tools such as VCS. Experience with Liberty file format and creating timing/power views. Knowledge of AMS verification environments is a plus. Strong scripting skills in Tcl, Perl, and/or Skill for automation. Excellent problem-solving, collaboration, and communication skills.