175 Analog Layout Jobs - Page 7

Dear Candidate We have immediate job openings for Analog layout and design openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Analog layout exp Skills Required: Analog Layout design and IO design Good to Have: Exposure to Analog layout, EDA tools Thanks Gayathri

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida

Greetings from ||Thundersoft|| We are looking for Cutsom Layout engineers with an exposure of Custom layout and having experience in GF 22nm FDSOI technology node

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Responsibilities: Must have solid understanding of analog & mixed signal design fundamentals Design of basic analog IPs like LDOs, DC-DC converters, ADC/DACs, PLLs,Oscillators, Temperature sensors, Bandgap references and voltage monitors. Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL,DLL, Phase Interpolator, DFE and FFE Working Experience in Die to Die interconnect high speed IO designs, HBM, DDRand UCIe protocols. Hands on experience on lower FINFET technology nodes Basic analog layout knowledge especially with FINFET technology Expertise in following tools and standards: Cadence and Synopsys mixed signal design tool flow Requirements: The Candidate should have at least 4 years of experience in Analog circuit designand be able to work independently Cadence and Synopsys mixed signal design tool flow Preferred Qualifications: Bachelors or masters degree in electrical engineering or Electronics & Communications.

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will be responsible for developing and configuring software systems, either end-to-end or for specific stages of the product lifecycle. Your typical day will involve collaborating with various teams to ensure that the software meets the required specifications and quality standards, while also applying your knowledge of technologies and methodologies to support the project effectively. You will engage in problem-solving activities and contribute to key decisions that impact the project and the team, ensuring that all deliverables align with client expectations and project goals. Roles & Responsibilities:Title:SRAM Layout Responsibilities:Individual contribution to SRAM Layout IP development Skill - Expected to be an SME, collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Facilitate knowledge sharing and mentoring within the team to enhance overall performance.- Monitor project progress and ensure timely delivery of milestones while maintaining quality standards. Professional & Technical Skills: Requirements:- SRAM IP Layout development experience. Familiar with virtuoso and calibre tools. Good to have:- Experience in SRAM layout IP development, leafell/block development from scratch. Must To Have Skills: Proficiency in Analog Layout.- Strong understanding of software development methodologies and best practices.- Experience with software configuration management tools.- Ability to analyze and troubleshoot complex software issues.- Familiarity with various programming languages and frameworks relevant to software development. Additional Information:Experience:- 2 years to 6 years. Qualifications:B.Tech/B.E/M.Tech/M.E - The candidate should have minimum 5 years of experience in Analog Layout.- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to perform maintenance and enhancements, ensuring that the application meets the highest standards of quality and functionality. You will also be responsible for developing new features and addressing any issues that arise, contributing to the overall success of the projects you are involved in. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Mentor junior team members to enhance their skills and knowledge.- Continuously evaluate and improve development processes to increase efficiency. Professional & Technical Skills: -Strong GPIO layout skills-Experience in advanced nodes in IC layout, including 28nm, 22nm, 14nm, 8nm, 5nm and below.-Experience in IC layouts with frequencies up to 40GHz.-Experience in critical IC layouts, including GPIO Library, ESD Cell and so on.-Working knowledge in Linux-Proficiency in CAD tools including Cadence Virtuoso, Calibre LVS, DRC, and SkillCad.-Excellency in communications skills in the form of verbal, email, and in documentations.-Be able to work independently.-Good to have experience to lead a small team and tapeout an analog IC.- Must To Have Skills: Proficiency in Analog Layout.- Strong understanding of circuit design principles and methodologies.- Experience with layout tools such as Cadence or Mentor Graphics.- Familiarity with design for manufacturability and reliability.- Ability to troubleshoot and resolve layout-related issues effectively. Additional Information:- The candidate should have minimum 5 years of experience in Analog Layout.- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Analog Layout Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will engage in the development and configuration of software systems, either managing the entire process or focusing on specific stages of the product lifecycle. Your day will involve collaborating with team members, applying your expertise in various technologies and methodologies, and ensuring that the software solutions meet client needs effectively and efficiently. You will also be responsible for troubleshooting issues and implementing improvements to enhance system performance and user experience. Roles & Responsibilities:- Expected to perform independently and become an SME.- Required active participation/contribution in team discussions.- Contribute in providing solutions to work related problems.- Facilitate knowledge sharing sessions to enhance team capabilities.- Mentor junior team members to foster their professional growth. Professional & Technical Skills: - Must To Have Skills: Proficiency in Analog Layout.- Strong understanding of circuit design principles and methodologies.- Experience with layout tools and design software.- Ability to analyze and optimize layout for performance and manufacturability.- Familiarity with design verification and validation processes. Additional Information:- The candidate should have minimum 3 years of experience in Analog Layout.- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Lead Project Role Description : Develop and configure software systems either end-to-end or for a specific stage of product lifecycle. Apply knowledge of technologies, applications, methodologies, processes and tools to support a client, project or entity. Must have skills : Analog Layout Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Lead, you will engage in the development and configuration of software systems, either managing the entire process or focusing on specific stages of the product lifecycle. Your day will involve collaborating with team members, applying your expertise in various technologies and methodologies, and ensuring that the software solutions meet client needs effectively and efficiently. You will also be responsible for troubleshooting issues and implementing improvements to enhance system performance and user experience. Roles & Responsibilities:- Expected to perform independently and become an SME.- Required active participation/contribution in team discussions.- Contribute in providing solutions to work related problems.- Facilitate knowledge sharing sessions to enhance team capabilities.- Mentor junior team members to foster their professional growth. Professional & Technical Skills: - Must To Have Skills: Proficiency in Analog Layout.- Strong understanding of circuit design principles and methodologies.- Experience with layout tools and design rule checks.- Ability to analyze and optimize layout for performance and manufacturability.- Familiarity with various fabrication processes and their impact on layout design. Additional Information:- The candidate should have minimum 3 years of experience in Analog Layout.- This position is based at our Bengaluru office.- A 15 years full time education is required. Qualification 15 years full time education

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr/ Staff Analog Layout Engineers: 7nm/ Lesser with DDR Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 5-8 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking a highly skilled Analog Mixed-Signal (AMS) Layout Engineer with proven expertise in 7nm or smaller technology nodes , FinFET architecture , and DDR interface layouts . The ideal candidate will work closely with design teams to deliver high-performance, low-power, and area-efficient layouts for cutting-edge semiconductor products. Key Responsibilities Design and develop full-custom AMS layouts for high-speed and low-power circuits in 7nm or below process nodes . Perform layout design for FinFET devices , ensuring optimal device matching, symmetry, and parasitic control. Implement layout for DDR interfaces (DDR3/DDR4/LPDDR/DDR5) including IOs, PHY blocks, and termination circuits. Conduct layout verification (DRC/LVS/ERC/ANT checks) using industry-standard EDA tools. Collaborate with circuit designers to meet performance, power, and area (PPA) targets. Optimize layouts for signal integrity, IR drop, electromigration , and manufacturability. Participate in design reviews and provide feedback on floorplanning, routing strategies , and parasitic extraction (PEX) results. Ensure compliance with foundry process design kits (PDK) and fabrication guidelines. Required Skills & Qualifications Bachelors or Master’s degree in Electronics, Electrical Engineering, or VLSI Design. 5-8 years of experience in AMS layout engineering. Hands-on experience with 7nm, 5nm, or advanced FinFET nodes in high-volume production. Strong knowledge of DDR interface layouts and signal integrity considerations. Proficiency in Cadence Virtuoso, Mentor Calibre, Synopsys IC Validator , or equivalent tools. Deep understanding of layout techniques for analog, digital, and mixed-signal blocks (e.g., PLLs, SerDes, ADC/DAC, IOs). Experience with power distribution, shielding, and ESD structures . Excellent problem-solving skills.

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 3-5 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking an Analog Mixed-Signal (AMS) Layout Engineer with deep expertise in 7nm or smaller process nodes , FinFET technologies , and high-speed layout design . The ideal candidate will have hands-on experience in complex analog, digital, and mixed-signal layouts, ensuring optimal performance, power, and area for cutting-edge semiconductor products. Key Responsibilities Perform full-custom Analog layout design for AMS circuits in advanced nodes (7nm or below). Work on FinFET device layouts , ensuring compliance with foundry-specific DRC/LVS requirements. Design high-speed analog/mixed-signal blocks such as SerDes, PLL, ADC/DAC, LDO, and other high-performance IPs. Collaborate with circuit designers to understand schematic intent and translate it into optimized physical layouts. Execute layout parasitic extraction (PEX) and work closely with verification teams for post-layout simulations. Ensure electromigration (EM), IR drop, and signal integrity compliance in layouts. Follow design-for-manufacturability (DFM) guidelines to maximize yield. Debug and resolve LVS/DRC violations in advanced technology nodes. Required Skills & Qualifications Bachelors/Masters in Electronics, VLSI, or related field . 3+ years of relevant AMS layout experience (7nm or smaller preferred). Proven expertise in FinFET layout design . Experience with high-speed analog/mixed-signal IPs (SerDes, PLLs, ADC/DAC, PHYs). Strong knowledge of Cadence Virtuoso, Calibre, Assura , or equivalent tools. Familiarity with PEX, LVS, DRC, ERC verification flows. Solid understanding of layout-dependent effects (LDEs) in advanced nodes. Strong collaboration skills with designers and verification engineers.

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Hands on with any of the spice simulators (Hspice/ Spectre)

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor's or Master's Degree.

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

Job Title: Senior EDA Engineer Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. Troubleshoot issues related to PDK integration, OA database consistency, schematic layout synchronization, and environment setups. Document technical processes, create reusable automation scripts, and contribute to team best practices. Collaborate with AI and software teams to integrate EDA tools into our AI co pilot platform and support continuous improvement of design automation. Required Skills & Experience: 3–8 years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. Proven experience managing and customizing CDF files for parametric device libraries in Cadence. Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). Strong UNIX/Linux command-line skills and scripting abilities. Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). Excellent communication skills and ability to operate effectively in a startup team environment. Preferred Qualifications: Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains. Experience with Spectre, ADE simulation, and analog verification flows. Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. Familiarity with AI/ML integration in design tools is a plus.

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. - Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team - Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. - Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. - Should have worked on and top-level integration - Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates. - Should have a good understanding of ESD, latch-up, EM, and strong skills debugging DRC, LVS, and antenna errors. - Job Complexity: Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise. - Supervision: Determines methods and procedures on new assignments and may coordinate activities of other personnel (Team Lead). - Experience with Cadence tools and TSMC processes are preferred .

Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. NAND Flash Design knowledge is plus Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including DLL, Rx, Tx and clocking circuits Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good automation & scripting knowledge is plus.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Analog layout designer providing onsite support for advanced nodes, working with global layout and design team. - Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team - Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout. - Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc. - Should have worked on and top-level integration - Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates. - Should have a good understanding of ESD, latch-up, EM, and strong skills debugging DRC, LVS, and antenna errors. - Job Complexity: Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise. - Supervision: Determines methods and procedures on new assignments and may coordinate activities of other personnel (Team Lead). - Experience with Cadence tools and TSMC processes are preferred