84 Analog Layout Jobs - Page 4

About The Role : The candidate will be expected to perform Development and support for DRC/LVS/PEX/PERC runset(ruledeck) generation on Intel's process. Development/support of ICV/Calibre/Pegasus/PVS runset (rule deck) for DRC/LVS/PEX/PERCConduct the L0QA of the codes. Bring in run time efficiency, automation and solve customer issues on rusets. Develop and maintain DRC/LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Qualifications Candidate needs to have:- B.tech or M.tech with 8+ years of experience in DRC/LVS/PEX/PERC runset development/QA on ICV/Calibre/Pegasus tools/flow.- Strong CMOS concepts- Strong debugging and scripting skills- Strong team working and leadership skills.- Layout tools:Virtuoso, CalibreDRV, IC Work Bench- Runset Development:Calibre, PVS, ICV, Pegasus- Scripting :Unix, Perl, Python or TCL Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

• 5+ years of EXP. in Analog Layout • Hands-On with CAD tools like Cadence Virtuoso XL, PVS/Calibre or Synopsys IC Validator, StarRC • Proficient at debugging/fixing LVS/DRC errors • EXP. with synthesis/advanced P&R (Innovus) is a plus Required Candidate profile • Work with circuit designers to complete the Physical Layout & Verification of High-Performance, Low-Power AMS CMOS IC's. • Solid understanding of semiconductor manufacturing process & DFM techniques

About The Role : Require Extraction expert with 8+ years' experience. The candidate will be expected to perform Development/support for extraction solutions for gate level and/or transistor level to build high quality PDK on STARRC/QRC. Development/support of ICV/Calibre/Pegasus runset (rule deck) for parasitic extraction, correlate parasitic coming from different extraction flows, assume ownership of entire LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Candidate is expected to have great stake holder management and leadership skill. Qualifications B.tech or M.tech with 8+ years of experience in runset development/QA on ICV/Calibre/Pegasus tools/flow. Expertise in Parasitic extraction tools like StarRC, QRC , xACT. Strong debugging and scripting skills. Strong team working and leadership skills. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Job Description Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience: TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor: Cadence Virtuoso L, XL Physical verification: DRC,LVS,Calibre Secondary Skills IO layout

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Has more than a year of relevant work experience. Solid understanding of programming concepts, software design and software development principles. Consistently works to direction with minimal supervision, producing accurate and reliable results. Individuals are expected to be able to work on a range of tasks and problems, demonstrating their ability to apply their skills and knowledge. Organises own time to deliver against tasks set by others with a mid term horizon. Works co-operatively with others to achieve team goals and has a direct and positive impact on project performance and make decisions based on their understanding of the situation, not just the rules. Skills (competencies) Verbal Communication

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree in electrical/Electronic Engineering. To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm , 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification :DRC, LVS, Calibre Secondary Skills IO layout

Job Title: Analog Circuit Design Engineers Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks Design of SERDES blocks like Transmitters, Receivers, Equalizers, Calibration and compensation blocks.

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 6-8 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python ,SKILL and/or TCL Environment: Professional knowledge related to incumbent's function/business unit and its processes.Communication/Negotiation: Advise other professionals. Effectively utilize group dynamics. Negotiate to define approaches and goals.Problem Solving: Recognize complex problems related to functional objectives. Analyze situations and implement solutions, or develop new system elements, procedures or processes. Creativity and judgment applied to developmental work on different projects within the business environment. Contribution/Leadership:Provides ongoing technical /operational guidance to lead professional work teams, conducts special projects, or manages department(s) (national or international). Understand department/ functional mission and vision. Defines and decides objectives within specified business concept or project and may have responsibility for tools and assigned resources. Utilizes expertise to directly influence people outside department or function. Sometimes no precedent exists.Impact on Business/Scope:Accountable for department results and for activities and/or projects involving multi-functional teams. Regularly participates in overall functional program planning. Activities are subject to business measurements, impact customer satisfaction, and impact project costs or expenses.

Responsibilities 1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing SKILL/PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes:3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.