108 Analog Layout Jobs - Page 4

Analog layout design requires knowledge of designing layouts of complex VLSI (very large scale integration) circuits using graphic editing tools in the Analog domain. A major portion of the job is in the creation of new physical design data from concepts, partial schematics, or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Your Role and Responsibilities Hands-on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below , and also take leadership roles in delivery of IPs. Work on Floor planning, power design, signal routing strategy, EMIR awareness, and parasitic optimizations . Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. Participate in building and enhancing layout flow for faster, higher quality design process. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks. Collaborate with Circuit Designers to solve challenging problems. Writing SKILL/PYTHON scripts to automate repetitive tasks. Work with Place and Route engineer to integrate custom macros into the top level. Able to perform design reviews across global teams. Work closely with required global teams to ensure the success of the whole product. Leadership in delivery of macros we plan to own from India. Job Requirements Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers , etc. Experience in designing layouts for high-speed circuits is a plus. Layout experience in the following technology nodes: 3nm, 5nm, and 7nm FinFET . Good team worker with multi-discipline, multi-cultural, and multi-site environments. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability, and failure mechanisms. Good problem-solving skills are essential where problems are analyzed upfront, identifying gaps, and providing optimum solutions. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise The Analog layout design engineer with experience in next-generation Ultra high-speed serial IO link (HSS) interface for Cognitive, ML, DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high-speed 32G/50G/112G IO link interfaces . Preferred Technical and Professional Experience Experience in 7 and 14 nm analog layout design . Working on Cutting edge technology and HSS domain. Quick learner, deep layout design knowledge, problem-solving skills, and good communication skills with cross teams across the Geos.

The Opportunity Were looking for the Wavemakers of tomorrow. Custom Layout / High-Speed Analog Layout Engineer Alphawave IP builds industry-leading wired connectivity solutions that enable data to travel faster, more reliably, and with higher performance at lower power. Our technology is embedded in leading-edge semiconductors built to power global network and computer systems. It is an essential part of the core infrastructure enabling next generation services in data centers, artificial intelligence, 5G wireless infrastructure, data networking, autonomous vehicles, and solid-state storage. The Opportunity The Alphawave IP team combines technologists from different disciplines who come together with a shared passion for electronics, software, and communication technology. We look for individuals with a deep desire to build great products and we value collaboration, curiosity, and a commitment to solving hard problems. The Alphawave Custom Layout team is composed of a group of highly technical, innovative, and passionate engineers, collaborating to develop the analog layouts and architectures for our world class high-speed SerDes IP s. What You ll Do Custom analog layout design for industry leading high speed Serdes architectures Working in leading edge semiconductor nodes and cad tools including latest 3nm node Detailed collaboration in optimizing layouts with analog design team Floor-planning Perform physical verification (DRC,ANT,LVS,ERC, ) Development and maintenance of layout software automation capabilities Work with a team of world-class engineers who are willing to help when needed and are happy to receive help when offered What You ll Need Bachelors in Electrical/Computer Engineering, EngSci, or equivalent Familiarity with high-speed analog layout, electronics and CMOS transistors Bonus points if you have worked in recent FinFet technologies (7nm, 5nm, etc) Minimum of 2 years of custom layout experience The position is located in Vancouver 5+ years of experience is preferred About You Excellent communication skills Able to listen to and appreciate ideas and opinions that differ from yours Extremely detail oriented Superb analytical and problem-solving skills Drives for consistency Takes personal pride in high standard of outputs Self-motivated and self-managing

The Opportunity Were looking for the Wavemakers of tomorrow. Custom Layout / High-Speed Analog Layout Engineer Alphawave IP builds industry-leading wired connectivity solutions that enable data to travel faster, more reliably, and with higher performance at lower power. Our technology is embedded in leading-edge semiconductors built to power global network and computer systems. It is an essential part of the core infrastructure enabling next generation services in data centers, artificial intelligence, 5G wireless infrastructure, data networking, autonomous vehicles, and solid-state storage. The Opportunity The Alphawave IP team combines technologists from different disciplines who come together with a shared passion for electronics, software, and communication technology. We look for individuals with a deep desire to build great products and we value collaboration, curiosity, and a commitment to solving hard problems. The Alphawave Custom Layout team is composed of a group of highly technical, innovative, and passionate engineers, collaborating to develop the analog layouts and architectures for our world class high-speed SerDes IP s. What You ll Do Custom analog layout design for industry leading high speed Serdes architectures Working in leading edge semiconductor nodes and cad tools including latest 3nm node Detailed collaboration in optimizing layouts with analog design team Floor-planning Perform physical verification (DRC, ANT, LVS, ERC, ) Development and maintenance of layout software automation capabilities Work with a team of world-class engineers who are willing to help when needed and are happy to receive help when offered What You ll Need Bachelors in Electrical/Computer Engineering, EngSci, or equivalent Familiarity with high-speed analog layout, electronics and CMOS transistors Bonus points if you have worked in recent FinFet technologies (7nm, 5nm, etc) Minimum of 2 years of custom layout experience The position is located in Vancouver 5+ years of experience is preferred About You Excellent communication skills Able to listen to and appreciate ideas and opinions that differ from yours Extremely detail oriented Superb analytical and problem-solving skills Drives for consistency Takes personal pride in high standard of outputs Self-motivated and self-managing Diversity & Inclusivity Alphawave IP is based out of one of the most diverse countries in the world. This includes differences related to race, ethnicity, national origin, gender, gender expression and presentation, sexual orientation, religion, age, ability and socioeconomic status. To us, diversity is one our strongest assets to our organization. We commit ourselves to promoting the recognition and appreciation of our diverse and rich culture. We believe that it is critical to our success to promote freedom of thought and opinion in a respectful environment. The decisions we make are rooted by respectfully considering each other s thoughts and opinions and by working towards a greater common goal, saving lives. Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Lead/Senior Analog Mixed-Signal (AMS) Engineers Layout / Verification / Design Locations: Noida | Bangalore | Hyderabad Experience: 7-12 Years Domain: Semiconductor | Analog Mixed-Signal | Custom IP & SoC Design Role Overview: We are hiring skilled and experienced professionals across AMS Layout , AMS Design , and AMS Verification disciplines to join our high-performance analog design team. You will contribute to the development of high-precision, low-power analog and mixed-signal IPs and subsystems targeted at next-generation SoCs in automotive, networking, and consumer electronics domains. Open Positions: Position #1: AMS Layout Engineer Responsibilities: Perform custom layout design of analog and mixed-signal circuits (e.g., ADCs, PLLs, LDOs, Bandgap, Bias, SerDes). Ensure layout quality, LVS/DRC clean , and meet area/power/performance targets. Work closely with circuit designers for floorplanning and layout optimization. Experience in FinFET nodes (e.g., 7nm/5nm) is a strong plus. Tools & Skills: Cadence Virtuoso (Layout XL), Calibre (LVS/DRC), PVS, Assura Strong grasp of matching, isolation, shielding, and analog layout best practices Position #2: AMS Design Engineer Responsibilities: Design and implement key analog/mixed-signal blocks such as amplifiers, voltage regulators, PLLs, SERDES, data converters, and ESD protection. Drive top-down design , simulation, and verification from spec to tape-out. Perform circuit simulation, characterization, and corner analysis . Tools & Skills: Cadence Spectre, Eldo, HSPICE, MATLAB, ADE-XL Good understanding of noise, mismatch, stability, and PVT simulations Position #3: AMS Verification Engineer Responsibilities: Develop AMS simulation environments integrating digital RTL and analog behavioral models. Use mixed-signal verification methodologies to validate complex AMS SoC subsystems. Support behavioral modeling (Verilog-A/AMS) and co-simulation using tools like Xcelium or AMS Designer. Tools & Skills: Verilog-AMS, SystemVerilog, UVM-MS, Cadence AMS Designer, Spectre AMS, Xcelium Knowledge of DFT hooks in analog blocks , test modes, and power intent is a plus Interested? Apply or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Long Description Annual maintenance contract preparation and preventive maintenance of QC and IPQA instrument as per approved procedure. Breakdown handling of QC and IPQA instrument as per approved procedure. Upkeep the records of preventive maintenance and breakdown in SAP. Qualification of new instruments and SOP preparation. To participate in failure investigation related to malfunctions. To impart training to the analysts for instruments maintenance and troubleshooting. Co-ordination with vendor service engineer of service /breakdown related activities. To maintain GMP in QC laboratory, Real time documentation. Computer system validation of laboratory instruments. Execution and implementation of quality system in laboratory. Taking part in internal calibration, out-side calibration and reviewing calibration data. Taking part in instrument cleaning maintain & Maintenance of all laboratories indents. QAMS, Caliber-e-log related activities SAP Bill & invoice clearance PO & PR related activity software handling EDMS ,SAP, caliber E log, QAMS, LIMS. etc. Competencies Innovation & Creativity Result Orientation Collaboration Customer Centricity Developing Talent Stakeholder Management Strategic Agility Process Excellence Education Graduation in Mechanical Engineering Work Experience 7 to 8 Years of experience in Quality Control as Instrument Engineer

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Mandatory Skills Experience in schematic design, layout and technical documentation Experience in designing and verifying analog layouts, including power driver analog designs with multilayer layout. Experience in CAD tools (Altium),creation for library ,symbol, footprint and database addition Good in PCB fabrication principles/Process Sounds in interface drawing and ECU and PCB drawing creation Experience in PCB level testing Tool Skills Altium, Auto-CAD Additional Skills Troubleshooting issues with electronic circuits and identifying the root cause of the issue. Familiarity with electrical test equipment including oscilloscopes, signal generators, spectrum analyzers, network analyzers, and multimeters.

You are a skilled Layout Engineer with 3-6 years of experience, specializing in Analog and Mixed-Signal IP layout. You have a background in Electronics or Electrical Engineering, holding a B.Tech or M.Tech degree. You possess a strong understanding of high-speed analog layout and have a solid grasp of CMOS and FinFET layouts. Your expertise extends to using CAD tools such as Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT. You are adapt at working independently, determining and developing solutions with minimal supervision. You frequently collaborate with senior personnel and are proactive in learning new technologies, demonstrating excellent analytical and problem-solving skills. Your strong communication skills enable effective interaction with internal development teams. What You'll Be Doing: Developing physical layout of high-speed Analog Integrated Circuits for the Analog and Mixed Signal IP group. Collaborating with a team of Analog/Mixed Signal Custom Layout Design Engineers on SerDes and Analog Mixed Signal IP blocks. Using advanced floor-planning techniques to optimize layout designs. Performing verification flows and ensuring compliance with DRC/LVS, LPE standards. Debugging and troubleshooting layout issues, utilizing your analytical skills. Providing regular updates to the manager on project status and networking with internal and external personnel. The Impact You Will Have: Contributing to the development of high-performance silicon chips that drive modern technology. Enhancing the reliability and efficiency of Analog and Mixed-Signal IP blocks. Ensuring the successful integration of high-speed signal layouts in cutting-edge applications. Improving the verification and validation processes through meticulous layout designs. Supporting the continuous innovation of Synopsys product offerings. Playing a key role in the development of next-generation electronic devices. What You'll Need: Experience in Analog Mixed-signal IP layout and verification of high-speed analog layout. Advanced understanding of Deep submicron effects and mitigation techniques. Expertise in CMOS and FinFET layouts and process technology. Familiarity with ESD and latchup layout design considerations. Proficiency in CAD tool usage, including Custom Designer/Cadence Virtuoso, Calibre, ICV, and STAR-RCXT.

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and physical design teams to optimize layout for performance, area, and reliability. Ensure adherence to foundry DRC/LVS/ANT/ERC/ESD guidelines and support closure of physical verification issues. Drive layout automation and CAD tool flows to improve efficiency and quality. Conduct design reviews and provide mentorship to junior layout engineers. Manage project schedules, resource planning, and risk mitigation strategies. Interface with external stakeholders including foundry, EDA vendors, and cross-functional teams. Required Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. 8+ years of hands-on experience in analog layout and team management. Proven track record of delivering production-quality analog/mixed-signal layouts in advanced nodes (e.g., 28nm, 16nm, 7nm, or FinFET technologies). Strong knowledge of parasitic extraction, EM/IR analysis, and layout-dependent effects (LDE). Proficient in layout tools such as Cadence Virtuoso, Calibre, Assura, and Mentor Graphics. Experience in team leadership, mentoring, and performance management. Excellent communication, documentation, and project management skills. Preferred Skills: Prior experience working in a fabless semiconductor environment. Knowledge of ESD protection, latch-up rules, and analog reliability concerns. Exposure to automotive, medical, or other high-reliability standards is a plus. What We Offer: Competitive compensation and benefits. Opportunity to work on leading-edge semiconductor technology. Collaborative and inclusive work environment. Professional development and career growth. Interested candidates can share their resumes to shubhanshi@incise.in

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Layout. Experience3-5 Years.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualification Minimum 5 years experience in a hands-on PDK role Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna". As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools Support the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts Collaborate with tool vendor and foundries for tools and flow improvements Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design Proficiency in one or more of the programming/scripting languages- , Python, Unix, Perl, and TCL. Good communication skills and ability to work collaboratively in a team environment Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational Requirements RequiredBachelor's, Electrical Engineering Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus- nanotime, xa/spectre, liberate, primelib, totem Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Details: : Intel is a leader in the wireless communication industry, offering products that set the benchmark for performance and innovation. We are seeking a motivated Junior SerDes PHY Integration Engineer to join our team. In this role, you will focus on integrating physical layer components for high-speed SerDes systems, playing a crucial part in ensuring their performance and reliability.Key Responsibilities:SerDes PHY IntegrationsSupport the integration of the physical layer for SerDes systems, including transmitter and receiver architectures, equalization techniques, and signal integrity.Simulation and ValidationAssist in conducting simulations using MATLAB and Python, along with lab testing, to validate the performance and compliance of the SerDes PHY, optimizing it for high-speed data transmission.Calibration TechniquesHelp integrate calibration methods to enhance the performance of the SerDes PHY, ensuring high-quality data transmission.CollaborationWork collaboratively with cross-functional teams, including digital design, hardware, and software, to ensure seamless integration of the PHY layer into the overall SerDes system.DocumentationContribute to maintaining detailed and up-to-date documentation of design specifications, test plans, and results.Problem-SolvingAssist in addressing and resolving technical issues related to the SerDes PHY, ensuring optimal performance.Quality AssuranceSupport the implementation of quality control measures and best practices to ensure the reliability and robustness of the SerDes PHY.Develop SERDES TestsParticipate in the development of comprehensive tests to support integration efforts, including writing scripts for software and firmware in Intel's test environment. Qualifications: Bachelor's degree in Electrical Engineering; a Master's degree in a relevant field is a plus.Passion for lab work, collaboration, and solution development.Familiarity with scripting and programming languages such as C, C#, MATLAB, and Python.Experience in silicon development and SerDes technologies is beneficial.Strong problem-solving abilities and analytical skills.Self-motivated and capable of executing tasks in uncertain environments.Demonstrated ability to contribute effectively in a matrix organization. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

PROFILE : Dedicated and detail-oriented Hardware Design Engineer with over 10+ years of experience in designing and implementing advanced electronic systems. Skilled in hardware board and systems design, with a strong experience of delivering innovative solutions and high-quality products. SKILL SET : - Designed and implemented circuit boards for next-generation electronic products, ensuring optimal performance and functionality. - Lead the design and development of complex hardware systems, including schematic design, PCB layout, and hardware bring-up. - Good background in both digital and analog circuit design, with a focus on high-speed interfaces like PCIe, USB-C, SATA, Ethernet, and various types of DDR (DDR3, 4, 5) memory. Also extends to low-speed communication protocols such as USB 2.0, UART, RS232, RS422, I2C, SPI, & CAN - Collaborate with cross-functional teams to define system requirements, architecture, and design specifications. - Conduct feasibility studies and risk assessments to ensure hardware designs meet performance, cost, and schedule requirements. - Manage team members, providing guidance on design best practices, tools, and methodologies. - Perform detailed design reviews, testing, and validation of hardware prototypes to identify and resolve design issues. - Work closely with suppliers and manufacturing partners to ensure the successful ramp-up and production of hardware products. - Lead troubleshooting efforts to identify and resolve hardware issues in the field, providing timely and effective solutions. - Stay up to date on industry trends and emerging technologies to drive innovation and improvement in hardware design practices. - Support product lifecycle management activities, including design updates, obsolescence management, and product end-of-life planning. - Communicate effectively with stakeholders, including management, customers, and partners, to ensure alignment on project goals, timelines, and deliverables. - Experience working on projects throughout the hardware design cycle, including testing mechanical enclosures and functionality for prototype and production designs, as well as performing and updating design changes during tooling. - Proficient in preparing design-related documents such as preliminary design reports, critical design reports, requirement capture documents, test plans, and assembly instructions. WORK TOOLS : - Concept HDL, Or-Cad, DX Designer, Allegro Viewer, LT Spice, Hyper Lynx, Viewmate, Auto vue, Solid edge Viewer and Microsoft Office.

Senior AMS Layout Engineer with 8+ years of experience , specifically with FinFET and high-speed layout expertise , based in Noida About the Role We are seeking a highly skilled and experienced Senior AMS Layout Engineer to join our advanced silicon design team in Noida . This role involves the physical layout design of analog and mixed-signal circuits , with a focus on FinFET nodes and high-speed, high-performance designs for next-generation semiconductor products. As a senior member of the team, you will work closely with circuit designers, layout leads, and verification engineers to deliver high-quality, tape-out-ready layout that meets stringent performance, power, and area (PPA) goals. Key Responsibilities Ownership of layout implementation for analog, mixed-signal, and high-speed blocks such as PLLs, LDOs, SerDes, ADCs, and high-speed I/Os. Perform layout floorplanning , transistor-level layout, and block-level integration at advanced nodes (FinFET: 7nm, 5nm, 3nm preferred). Ensure DRC, LVS, ERC, and EMIR clean layout using industry-standard tools (Cadence Virtuoso, Assura, Calibre). Collaborate with circuit design teams to understand and implement layout constraints and critical matching, shielding, symmetry, and routing rules. Execute layout optimization for performance, area, and manufacturability. Guide and review work of junior layout engineers and assist in resolving technical challenges. Work closely with physical verification and post-layout simulation teams for signoff closure. Support tape-out and post-silicon debug, as required. Required Qualifications & Skills Bachelor's or Master's degree in Electronics , Electrical Engineering , or related fields. 8+ years of proven experience in analog and mixed-signal layout design . Strong hands-on expertise in FinFET layout (e.g., 7nm and below), including handling of high-speed analog and custom digital layouts. Proficiency with Cadence Virtuoso , Assura , Calibre , and physical verification tools. Solid understanding of layout-dependent effects (LDE) , parasitic-aware layout, electromigration, and IR drop considerations. Familiarity with high-speed design constraints such as matched routing, shielding, isolation, and power planning. Excellent team collaboration and communication skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: "¢ Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. "¢ 3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). SRAM Mask Layout Designer Qualcomm is a company of inventors seeking to revolutionize the CPU market in an age of new possibilities. Are you interested in joining Qualcomm"™s high performance CPU team as an SRAM Mask Layout Designer? You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. As a Mask Layout Designer, you will develop block or macro level layouts and floorplans for high performance custom memories according to project requirements, specifications, and design schematics. Minimum qualifications — 5+ years of experience and a high school diploma or equivalent — OR 5+ years experience and BS in Electrical Engineering — OR 3+ years experience and MS in Electrical Engineering — Direct experience with custom SRAM layout — Experience in industry standard custom design tools and flows. — Knowledge of leading-edge FinFET and/or nanosheet processes (5nm or newer). — Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. — Knowledge of all aspects of Layout floorplanning and hierarchical assembly. — Knowledge of Cadence Virtuoso and Calibre LVS/DRC. Preferred qualifications — Good understanding of device parasitics and reliability considerations during layout. — Good understanding of critical circuits and layout styles. — Ability to write Skill code for layout automation. — Knowledge of improving EMIR in layout. — Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Roles and Responsibilities — Design layout for custom memories and other digital circuits based on provided schematics. — Read and interpret design rule manuals to create optimal and correct layout. — Own the entire layout process from initial floorplanning to memory construction to physical verification. — Use industry standard verification tools to validate LVS, DRC, ERC etc. — Interpret the results from the verification suite and perform layout fixes as needed. — Provide layout fixes as directed by the circuit design engineers. — Work independently and execute memory layout with little supervision. — Provide realistic schedules for layout completion. — Provide insight into strategic decisions regarding memory layout and

Work Profile : - Work on development of custom Analog circuit boards for applications related to RF, interfaces etc. - Implement new features and bug fixes - Verify analog/mixed-signal integrated circuits - Develop test cases to verify new features and bug fixes - Review and update the user manuals for software tools. - Supporting digital modelling of analog circuits for mixed-signal verification - Creating design specifications and circuit schematics - Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team - Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements - Collaborate with others in the creation of technical reports, whitepapers, and user documentation Requisites : - EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges . - Strong knowledge of analog integrated circuit design fundamentals - Proven experience taking designs from concept to production - Experience in analog/mixed-signal IC design & verification - Understanding of BJT, CMOS and Op-Amp technologies. - Good understanding of analog/mixed-signal design flows (Cadence, Synopsys) - Transistor and system level simulation skills - Discrete time and continuous time signal processing skills - Strong lab and silicon validation skills - Verilog based digital design and test bench development, is a plus - Strong communication skills, both written and verbal

Profile : Dedicated and detail-oriented Hardware Design Engineer with over 10+ years of experience in designing and implementing advanced electronic systems. Skilled in hardware board and systems design, with a strong experience of delivering innovative solutions and high-quality products. Skill Set : - Designed and implemented circuit boards for next-generation electronic products, ensuring optimal performance and functionality. - Lead the design and development of complex hardware systems, including schematic design, PCB layout, and hardware bring-up. - Good background in both digital and analog circuit design, with a focus on high-speed interfaces like PCIe, USB-C, SATA, Ethernet, and various types of DDR (DDR3, 4, 5) memory. Also extends to low-speed communication protocols such as USB 2.0, UART, RS232, RS422, I2C, SPI, & CAN - Collaborate with cross-functional teams to define system requirements, architecture, and design specifications. - Conduct feasibility studies and risk assessments to ensure hardware designs meet performance, cost, and schedule requirements. - Manage team members, providing guidance on design best practices, tools, and methodologies. - Perform detailed design reviews, testing, and validation of hardware prototypes to identify and resolve design issues. - Work closely with suppliers and manufacturing partners to ensure the successful ramp-up and production of hardware products. - Lead troubleshooting efforts to identify and resolve hardware issues in the field, providing timely and effective solutions. - Stay up to date on industry trends and emerging technologies to drive innovation and improvement in hardware design practices. - Support product lifecycle management activities, including design updates, obsolescence management, and product end-of-life planning. - Communicate effectively with stakeholders, including management, customers, and partners, to ensure alignment on project goals, timelines, and deliverables. - Experience working on projects throughout the hardware design cycle, including testing mechanical enclosures and functionality for prototype and production designs, as well as performing and updating design changes during tooling. - Proficient in preparing design-related documents such as preliminary design reports, critical design reports, requirement capture documents, test plans, and assembly instructions.

Our vision is to transform how the world uses information to enrich life for all, Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever, For more than 45 years, Micron Technology, Inc has redefined innovation with the worlds most advanced memory and semiconductor technologies Were an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life, We are looking for Layout Design engineer at our Micron Technologys HBM Team in Hyderabad, India As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment, Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support, Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation, Responsible for on-time delivery of block-level layouts with acceptable quality, Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment, Guide junior team-members in their execution of Sub block-level layouts & review their work Contribute to effective project-management, Effectively communicating with Global engineering teams to assure the success of layout project, Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must, Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc , Good understanding of Analog Layout fundamentals (e-g , Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc ) Understanding layout effects on the circuit such as speed, capacitance, power and area etc , Ability to understand design constraints and implement high-quality layouts, Ability to understand design hierarchy and different architectures for Memory designs, Excellent command and problem-solving skills in physical verification of custom layout, Multiple Tape out support experience will be an added advantage, Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development, Excellent verbal and written communication skills, Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status, About Micron Technology, Inc, We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micronand Crucialbrands Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities ? from the data center to the intelligent edge and across the client and mobile user experience, To learn more, please visit micron /careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status, To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards, Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron,

Our vision is to transform how the world uses information to enrich life for all, Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever, For more than 45 years, Micron Technology, Inc has redefined innovation with the worlds most advanced memory and semiconductor technologies Were an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life, We are looking for Layout Design engineer at our Micron Technologys HBM Team in Hyderabad, India As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment, Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support, Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation, Responsible for on-time delivery of block-level layouts with acceptable quality, Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment, Guide junior team-members in their execution of Sub block-level layouts & review their work Contribute to effective project-management, Effectively communicating with Global engineering teams to assure the success of layout project, Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must, Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc , Good understanding of Analog Layout fundamentals (e-g , Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc ) Understanding layout effects on the circuit such as speed, capacitance, power and area etc , Ability to understand design constraints and implement high-quality layouts, Ability to understand design hierarchy and different architectures for Memory designs, Excellent command and problem-solving skills in physical verification of custom layout, Multiple Tape out support experience will be an added advantage, Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development, Excellent verbal and written communication skills, Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status, About Micron Technology, Inc, We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micronand Crucialbrands Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities ? from the data center to the intelligent edge and across the client and mobile user experience, To learn more, please visit micron /careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status, To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards, Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron,

Analog Design Engineer Skills & Experience Required: 5+ years of relevant experience. Has relevant knowledge and hands on experience of SerDes design at high data rates, up to 20Gbps. Study the assigned block, analyze the circuit carefully, and work on the hand analysis. Understand the required performance, the targeted specs and trade-off between different performance metrices. Write behavioral model of the circuit blocks for system-level simulations. Simulate and verifying designed schematics using Synopsys tools using circuit simulators. Debug to find out the root cause for any performance degradation. Being capable of solving all the faced issues. Working with layout team on layout optimization. Evaluate post layout performance using extraction tools (ICV and Calibre). Understand the interface with other blocks (if any) and work with other team members to optimize the interface. Coordinate and handling top-level simulations. Develop and executing characterization plans of the designed blocks, systems, and chips. Check the design reliability (EM/IR/Aging) using available tools. Do timing models using custom static timing analysis tools. Deliver the corresponding documentation as per the design process. Excellent knowledge of design/simulation tools such as Synopsys, Cadence and/or Mentor tools or any relevant tool. Good knowledge of any EM simulation tool. Good knowledge in behavioral modeling (Verilog, Verilog AMS). Very Good knowledge of custom timing static analysis tool (Synopsys NanoTime and SiliconSmart). Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaKolkata IndiaNoida S. KoreaSeoul Location - Bengaluru,Chennai,Kolkata,Noida