341 Analog Layout Jobs - Page 3

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

We are looking for Analog Layout Engineers who have FinFET exp Location: Hyderabad Exp: 4-7yrs NP: Immediate to 15 days If interested, please share your profile to my email naveen.a@modernchipsolutions.com

Role Overview: As a Senior Analog and Digital Mask Design Engineer at NVIDIA, you will be part of a dynamic team responsible for handling challenging analog circuit designs. Your primary focus will be executing IC layout of cutting-edge, high-performance CMOS integrated circuits in various foundry process nodes. You will play a key role in driving the identification and resolution of complex physical design issues, mentoring junior engineers, and ensuring design quality by adhering to industry best practices. Key Responsibilities: - Execute IC layout of high-performance CMOS integrated circuits in foundry process nodes ranging from 2nm to 7nm and lower, following industry best practices. - O...

Define the architecture and implement transistor-level design of analog and mixed-signal blocks for Power efficient Iot ICs. Perform pre- and post-layout simulations and analysis across PVT corners using industry-standard EDA tools Work closely with layout engineers to optimize performance, area, and noise/EMI sensitivity. Collaborate with cross-functional teams across design, verification, test, validation, Support silicon bring-up, characterization, and debug Produce high quality review and spec documents Promote IP reuse, documentation best practices, and patent/IP generation initiatives. Guide junior engineers as and when needed. Requirements M.E./M.Tech or Phd in Electronics Engineering...

Project Role : Analog Layout Engineer Project Role Description : Design the physical layout of analog circuits, ensuring proper component placement and routing for optimal performance. Address parasitic effects, signal integrity, and power distribution to meet design specifications. Collaborate to ensure the layout meets functional, electrical, and manufacturing requirements. Must have skills : Analog Layout Good to have skills : NA Minimum 12 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: As an Analog Layout Engineer, you will engage in the intricate process of designing the physical layout of analog circuits. A typical day involves ensur...

Project Role : Custom Software Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NA Minimum 3 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: Designing and developing Analog layouts for high-speed analog and mixed-signal IP blocks including SerDes, RX, TX, PLL,LDO,ADC, DAC and custom logic paths. Collaborating with a team of experienced layout engineers to deliver optimized, reliable, and manufacturable designs. Utilizing advanced CAD tools (Cus...

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Extensive PAD Ring and Top/Chip level layout experience. Good understanding of package/substrate design and package assembly rules related to flip chip designs, BGA, LFCSP etc. Experience in IO Pads, ESD clamps and Analog Mixed Signal IP layout Layout experience in the following technology nodes is a plus: 180, 40nm and 22nm GF

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years ...

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years ...

Role & responsibilities JobTitle : AnalogLayout_Engineers with SerDes HighSpeedCircuits Please find below JD Required Skills & Experience : 3to6YearsHyderabad Bangalore_Locations 4to6years of Experience in analog / customlayout , with a strong focus on SerDes / HighSpeed circuits . hands -on experience with TSMC / Samsung / Intel nodes ( 7nm , 6nm , 5nm or 3nm ). Deep understanding of layout-dependent effects (LDE), matching techniques, and parasitic extraction for high-speed circuits. Strong expertise in Cadence Virtuoso (XL/GXL) tools and Calibre / PVS verification tools. Experience with differential pair routing, impedance control, shielding, and clock distribution layouts. Knowledge of E...

Foundry Experience: TSMC 5nm/3nm is mandatory; Technical Skills: Verification flows: LVS, DRC, DFM, Antenna check, EMIR Recent Experience: Candidates must have hands-on experience with lower nodes in recent projects

5 to 10 years of experience in analog layout design. Proven experience in advanced nodes (7nm, 5nm, or below) is a must. Proficiency in layout tools such as Cadence Virtuoso, ICV, Calibre, Assura, etc Strong understanding of analog layout constraints and techniques for high-performance and low-noise designs. Preferred Skills: Experience in high-speed IO layout (eg, SerDes, DDR, PCIe). Exposure to MBCFET and FinFET layout challenges and solutions. Understanding of ESD and latch-up prevention techniques.

Radiant Semiconductors is looking for Physical Verification to join our dynamic team and embark on a rewarding career journey. Perform physical verification of semiconductor designs using CAD tools. Verify layout and design rules compliance. Conduct DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification. Analyze and debug physical verification errors and violations. Work with design and layout teams to resolve physical design issues. Implement and optimize physical verification methodologies. Generate and review physical verification reports. Stay updated with semiconductor manufacturing processes and technologies. Disclaimer : This job description has been sourced from a public...

1.should work on block level layouts for analog and mixed signal designs. 2. Having hands on top level placement (Module level) routing & verification 3. Should work on TSMC 40, 28 or 22nm Share the profile to : Anand.arumugam@modernchipsolutions.com

You will be responsible for the Analog Layout work, specifically focusing on TSMC 7nm technology and Serdes (Tx, Rx). Your role will involve designing and implementing analog layouts according to project requirements. **Key Responsibilities:** - Create analog layout designs based on TSMC 7nm technology - Implement Serdes (Tx, Rx) layouts as per project specifications - Collaborate with the team to ensure layout designs meet performance goals **Qualifications Required:** - Bachelor's degree in Electrical Engineering or related field - 4 to 10 years of experience in analog layout design - Proficiency in using layout design tools and software If you are interested in this position and meet the ...

Job Requirements Bachelor's or master's Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable : Mixed signal/analog/high speed layout, e.g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR & Self-heating...

Role Overview: As a Senior Analog Circuit Design Engineer at Eximietas Design, you will be responsible for designing analog and mixed-signal circuits. You should have a strong understanding of Analog & Mixed Signal Design fundamentals, including bandgap references and voltage monitors. Your role will involve implementing circuit designs for SERDES blocks like Transmitter, CTLE, SAL, DLL, Phase Interpolator, DFE, and FFE. Additionally, you will work on Die to Die interconnect high-speed IO designs, HBM, DDR, and UCIe protocols, with hands-on experience in lower FINFET technology nodes. Key Responsibilities: - Solid understanding of Analog & Mixed Signal Design fundamentals - Design implementa...

As a Layout Engineer at the India Design Center in Chennai, India, you will play a crucial role in the physical layout of pSemis handset, wireless infrastructure, and broadband integrated circuits using pSemis proprietary UltraCMOS process technology. Your responsibilities will include developing critical module level layout, ensuring on-time delivery of block-level layouts, optimizing layouts for performance and area, and verifying and cleaning DRC/LVS/ERC/ANT checks for layouts. You will work closely with global design teams in pSemi and take complete ownership of assigned layout tasks. Key Responsibilities: - Development of critical module level layout and full chip integration support - ...

You are an Experienced Layout Engineer sought by ACL Digital for their Bangalore location. Your role involves working with AMS/IO Memory Layout, specifically focusing on Lower nodes from TSMC and ESD Blocks. As a candidate, you are expected to have a Bachelor's or Master's Degree with 4 - 12 years of Analog Layout experience. Additionally, you should possess demonstrated leadership skills, including hiring, nurturing talent, leading project execution, and client/stakeholder management for at least 3 years. Your key responsibilities will include: - Full-custom circuit layout/verification and RC extraction experience - Experience in advanced technology node under TSMC - 32nm/28nm/16nm/14nm/7nm...

We are looking for a skilled professional with 5 to 7 years of experience to join our team as a Manager I - Capital and GTS Reporting in Bristol-Myers Squibb India Pvt. Ltd. Roles and Responsibility Manage and oversee the preparation of capital and GTS reports, ensuring accuracy and timeliness. Develop and implement effective reporting processes to meet business requirements. Collaborate with cross-functional teams to ensure seamless integration of reporting systems. Analyze and interpret complex data to provide insights for business decisions. Ensure compliance with regulatory requirements and industry standards. Lead and mentor a team of report preparers to enhance their skills and perform...

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualificatio...

Your role and responsibilities -Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. Required education Bachelor...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Analog Layout Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to perform maintenance and enhan...