84 Analog Layout Jobs - Page 3

About The Role Designs, develops, and builds digital circuits for custom blocks including SRAM, register files, memory compilers, and caches. Designs floorplans, performs circuit design, schematic entry, simulation for major blocks, and verifies functionality to optimize custom circuit for power, performance, area, timing, and yield goals. Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design. Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and memory circuit design issues. Optimizes performance, power, and area, reduce leakage of circuits, and drive characterization of individual memory instances and memory compilers. Works with architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities. Qualifications The candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum qualifications Must have a Bachelors (B.Tech) in Electronics or Masters (M.Tech) in Electrical, Microelectronics or VLSI Engineering. B.Tech with 8+ years and M. Tech with 6+ years' experience required. 6+ years' experience with scripting (Perl, tcl etc. 6+ years' experience in memory design convergence tools including formal equivalence verification, static timing methodology, electrical reliability and robustness analysis. 6+ years' experience with transistor level operation, memory bitcell design, design challenges under process variations and low power circuit techniques, Innovative architectural proposals, driving layouts and its driven decisions. Preferred Qualifications Some experience in scripting, compiler understanding and hands on experience in coding tilers. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

About The Role Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs.Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues.Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications Qualifications:B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience in high-speed analog circuit design, with a proven track record of successful projects.Expertise in designing and verifying analog circuits such as High-speed transmitter, recevier, amplifiers, PLLs, voltage regulators, and data converters.Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Cadence VLE/VXL, DRC/LVS/Antenna Block level layouts Physical verification of custom layout Analog/Custom layout with 3nm/5nm/7nm Must have 5+ years of experience

As a Custom Analog Layout Designer, you will focus on the physical implementation of high-performance analog circuits. You will work closely with design engineers to translate schematics into efficient layouts that meet performance, power, and area requirements. Key Responsibilities: Design custom layouts for analog and mixed-signal circuits. Ensure compliance with design rules and optimize for performance. Perform layout versus schematic (LVS) and design rule check (DRC) to ensure accuracy and manufacturability. Qualifications: Proficiency in layout tools like Cadence Virtuoso and strong understanding of layout techniques for analog design. Bachelor s degree in Electrical Engineering or related field.

**Responsibilities*: OnSemi is seeking a Staff Analog layout Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr MOS, AC-DC converters, LED drivers, SiC drivers, Switches and e-fuses for consumer, industrial and automotive applications In this role, you will focus on the following Produce high quality layout for complex AMS IP blocks (voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, drivers etc) + Contribute to area estimation and optimization, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc ), as well power analysis (EM / IR-Drop) + Contribute and support team in taping out high-performance microcontroller chip + Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD) + Develop scripts and methods for layout design automation \#LI-LK1 **More details about our company benefits can be found here:** https://www onsemi com/careers/career-benefits We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work

Interested candidates please forward resumes to: vlsi.team07@gmail.com looking for immediate to 1 month NP people.

Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Ability to understand design hierarchy and different architectures for Memory designs. Excellent command and problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent verbal and written communication skills. Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

As an Director-HBM Layout, you will work with an exceptionally talented, passionate core team based in India, lead the team to design for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. You will be collaborating with peer teams crossing Micron global footprint, to meet scheduled milestones in a multiple projects-based environment. Responsibilities Provide leadership in building and growing a Custom and Semi-custom layout team from the ground up to support Microns HBM team's requirement. Provide leadership in developing Custom and semicustom layout to meet schedule and milestone. Provide leadership in training the teams technical skills and cultural healthiness. Effectively communicating with global engineering teams to assure the success HBM roadmap. Organize, prioritize, and manage logistic on tasks and resource allocations for multiple projects. Manage performance and development of team members. Managing hiring and retention. As a critical member of the core HBM leadership team in India, contribute to the overall success of the Micron's HBM India operation. Qualification/Requirements 18 + year experience in analog/custom layout in advanced CMOS process, in various technology nodes (Planar, FinFET ) Minimum 4+ years people management experience. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Must have strong skills in layout and floor planning skills and manual routing. Strong ability to build, and continuously develop a premier analog/mixed-signal layout team. Experienced in managing multiple Custom IC layout projects. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design. The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment. Excellent verbal and written communication skills required. Independent with strong analytical skills, creative thinking and self-motivated. Capable of working in a cross functional, multi-site team environment in multiple time zones. Previous work experience in DRAM/NAND layout design is desirable however not mandatory. Strong passion and ability to attract, hire, retain engineers by motivating them and by inculcating innovation culture. Ability to collaborate with overseas Teams to define strategy, plan, and execute across the larger, global organization. Be accountable for the proper technical solutions implemented by your team. Expertise on people Management. Contributing to the development of new HBM, overall design, layout, and optimization of Analog / custom Layout

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Services Group, Engineering Services Group > Layout Engineer General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design. Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below. Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS. Basic understanding of IO/ESD designs. Knowledge on Basic SKILL/PERL. Capable of working independently and with team and getting work done with contract work force. The ability to work & communicate effectively with global engineering teams.

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Has more than a year of relevant work experience. Solid understanding of programming concepts, software design and software development principles. Consistently works to direction with minimal supervision, producing accurate and reliable results. Individuals are expected to be able to work on a range of tasks and problems, demonstrating their ability to apply their skills and knowledge. Organises own time to deliver against tasks set by others with a mid term horizon. Works co-operatively with others to achieve team goals and has a direct and positive impact on project performance and make decisions based on their understanding of the situation, not just the rules. Skills (competencies) Verbal Communication

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. What we need to see: 2+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. What we need to see: 2+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Analog Design and Verification I/O Library cells Follow Up Description: Development, implementation and verification of analog full custom circuit designs Development of architecture and circuit concepts under consideration of e.g. DfT, ESD, ... Dimensioning, simulation and optimization of circuits Functional and electrical verification of circuits (with automated test benches) Post layout verification/simulation (parasitics, I/R drop, current analysis, ...)

About The Role : Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. About The Role : - Grade Specific Is fully competent in it's own area and has a deep understanding of related programming concepts software design and software development principles. Works autonomously with minimal supervision. Able to act as a key contributor in a complex environment, lead the activities of a team for software design and software development. Acts proactively to understand internal/external client needs and offers advice even when not asked. Able to assess and adapt to project issues, formulate innovative solutions, work under pressure and drive team to succeed against its technical and commercial goals. Aware of profitability needs and may manage costs for specific project/work area. Explains difficult concepts to a variety of audiences to ensure meaning is understood. Motivates other team members and creates informal networks with key contacts outside own area. Skills (competencies) Verbal Communication

Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications. 1. Applies scientific methods to analyse and solve software engineering problems. 2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance. 3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers. 4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities. 5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. Job Description - Grade Specific Is highly respected, experienced and trusted. Masters all phases of the software development lifecycle and applies innovation and industrialization. Shows a clear dedication and commitment to business objectives and responsibilities and to the group as a whole. Operates with no supervision in highly complex environments and takes responsibility for a substantial aspect of Capgeminis activity. Is able to manage difficult and complex situations calmly and professionally. Considers the bigger picture when making decisions and demonstrates a clear understanding of commercial and negotiating principles in less-easy situations. Focuses on developing long term partnerships with clients. Demonstrates leadership that balances business, technical and people objectives. Plays a significant part in the recruitment and development of people. Skills (competencies) Verbal Communication

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications B.Tech / M.Tech/ Phd with with 3+ hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, recevier, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys.

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

About The Role : The candidate will be expected to perform Development and support for DRC/LVS/PEX/PERC runset(ruledeck) generation on Intel's process. Development/support of ICV/Calibre/Pegasus/PVS runset (rule deck) for DRC/LVS/PEX/PERCConduct the L0QA of the codes. Bring in run time efficiency, automation and solve customer issues on rusets. Develop and maintain DRC/LVS/extraction flow, working closely with various design/development groups. Perform in a dynamic and challenging environment with drive and creativity. Qualifications Candidate needs to have:- B.tech or M.tech with 8+ years of experience in DRC/LVS/PEX/PERC runset development/QA on ICV/Calibre/Pegasus tools/flow.- Strong CMOS concepts- Strong debugging and scripting skills- Strong team working and leadership skills.- Layout tools:Virtuoso, CalibreDRV, IC Work Bench- Runset Development:Calibre, PVS, ICV, Pegasus- Scripting :Unix, Perl, Python or TCL Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in theTechnology Development and Manufacturing Groupare part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

As an Analog Electronics Engineer at Articulus Surgical, you will be responsible for supporting the design and development of our products by creating and maintaining analog electronic systems. You will work closely with our engineering and design teams to ensure that our products meet the highest standards of quality and functionality. Your expertise in electronics components, design and debugging of electronic circuits, PCB design, fabrication and soldering, power electronics, as well as areas including communication protocols (EtherCAT, CAN, I2C, SPI), motor control systems, etc. will be vital in your role. Key Responsibilities : Analog Circuit Design : Collaborate on the design of precision analog circuits employing operational amplifiers, filters, and voltage regulators, with a focus on minimizing noise and ensuring high reliability in robotic systems. Power Electronics : Design and optimize power electronics circuits, including DC-DC converters, motor drivers, and power management systems, and ensure efficiency, thermal management, and reliability in critical robotic applications. Prototyping : Execute prototyping phases involving breadboarding and iterative refinement, implementing SMT components and ensuring signal integrity through use of intelligent system design. Testing and Debugging : Conduct comprehensive testing of analog systems, employing systematic debugging methods to identify and rectify issues, ensuring adherence to strict performance criteria. Documentation : Maintain documentation of analog system designs, including schematics, BOMs, and layout files, ensuring transparency in design decisions and facilitating efficient collaboration. Collaboration : Engage in interdisciplinary collaboration, communicating technical issues with software and hardware teams, facilitating the integration of analog systems into robotic platforms, and ensuring seamless functionality across subsystems. Research and Development : Stay updated on cutting-edge analog technologies, industry trends, and methodologies, actively contributing technical insights to inform research and development initiatives and enhance the technological capabilities of the company Requirements : BTech / MTech in Electronics Engineering, Electrical Engineering, Electronics & Instrumentation, Mechatronics, or allied disciplines. 2-4 years experience in analog systems design and development. Experience in the Medical Device industry or Robotics industry is an add on. Ability to design and debug analog and power electronics circuits, including component selection, schematic creation, and PCB design. Hands-on proficiency in the development and troubleshooting of analog systems. Experience in interfacing with analog components, including amplifiers, filters, and signal conditioning circuits. Knowledge of circuit protection elements for ESD, EMI, EMC protection. Knowledge of analog devices such as sensors, transducers, drivers, and actuators. Familiarity with fundamental analog concepts, including voltage/current measurement, impedance matching, and noise analysis. Understanding of communication protocols: EtherCAT, CAN, SPI, I2C. Strong analytical and problem-solving skills in the context of analog systems. Proficient in reading and interpreting analog schematics and data sheets. Capacity to adapt to a dynamic work environment, manage tasks effectively, and meet project deadlines. Inherent motivation for learning and contributing to a collaborative and excellence-driven team culture.

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts review critical items. Contribute to effective project-management. Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background BE or MTech in Electronic/VLSI Engineering 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm 5+ exp ****

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.

About The Role : Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications Qualifications: B.Tech 7+ years & M.Tech 5+ years or PhD having hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, receiver, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intels offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

About The Role : Role Purpose: A Business Finance Manager role requires working with cross-functional teams Do: - Co-own the financial plan of the portfolio along with the portfolio lead. - Revenue governance (including client interactions for deal closures and contracting; forecasting, revenue recognition) - Margin Governance (including cost take out initiatives, systemic and sustainable cost reduction analysis). - Working capital governance (including unbilled reduction, timely invoicing, and collection, improving debt ageing and PDD). - MIS for the business unit including cost pyramid analytics, revenue leakage vs order book. - Critical attributes to success would be strong communication, cadence, and resilience. - Commercial Structuring and Deal pricing for multiple lines of business