108 Analog Layout Jobs - Page 2

As an IC Layout Manager at Micron Technology, you will have the opportunity to lead a dedicated team in India focused on designing IC layouts for cutting-edge applications such as artificial intelligence and high-performance computing solutions like High Bandwidth Memory. Your role will involve collaborating with teams across Micron's global network to ensure the timely delivery of multiple projects. Your responsibilities will include building and developing a custom layout team to support Micron's DRAM layout requirements, overseeing the development of analog and custom layouts, and training team members in technical skills. Effective communication with engineering teams in different countries, organizing tasks and resource allocations, managing team performance, and contributing to the success of Micron's DRAM operations in India will be crucial aspects of your role. To be successful in this position, you should have at least 14 years of experience in analog/custom layout within advanced CMOS processes, with expertise in tools such as Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. Strong layout and floor planning skills, as well as experience in managing multiple custom IC layout projects, are essential qualifications. Additionally, you should possess excellent communication skills, the ability to work effectively in a fast-paced environment, and a passion for innovation and team development. Ideally, you should hold a BE or MTech in Electronic/VLSI Engineering. Previous experience in DRAM/NAND layout design is desirable but not mandatory. Your role will involve collaborating with overseas teams, defining strategies, and ensuring the successful implementation of technical solutions by your team. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovation and transformation in the data economy. Through a focus on customer needs, technology leadership, and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products that power advancements in artificial intelligence and 5G applications. If you are passionate about driving innovation, fostering team growth, and contributing to the evolution of information technology, consider joining Micron Technology and be part of a dynamic and forward-thinking organization. To learn more about Micron Technology, Inc. and explore career opportunities, please visit micron.com/careers. For any assistance with the application process or to request accommodations, please contact hrsupport_india@micron.com. Micron upholds a commitment to ethical labor practices and prohibits the use of child labor, adhering to all relevant laws and standards.,

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus.

As an IC Layout Manager at Micron Technology, you will have the opportunity to work with a talented core team based in India, focusing on designing IC layouts for applications such as artificial intelligence and high-performance computing solutions, including High Bandwidth Memory. Your role will involve collaborating with global teams to ensure the successful completion of multiple projects within scheduled milestones. Your responsibilities will include: - Building and growing a Custom layout team to support Micron's global DRAM layout requirements. - Developing Analog and custom layout designs to meet project schedules and milestones. - Training team members in technical skills and fostering a healthy team culture. - Communicating effectively with engineering teams across different regions to ensure project success. - Organizing, prioritizing, and managing tasks and resources for multiple projects. - Performance management and development of team members. - Leading hiring and retention efforts. - Contributing to the overall success of Micron's DRAM India operation. To qualify for this role, you should have: - 14+ years of experience in analog/custom layout in advanced CMOS processes. - Minimum 1+ year of people management experience. - Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS. - Strong skills in layout, floor planning, and manual routing. - Ability to build and develop a premier analog/mixed-signal layout team. - Experience in managing multiple Custom IC layout projects. - Motivation, attention to detail, and a systematic approach in IC layout design. - Excellent communication skills and the ability to work effectively in a team and fast-paced environment. - Strong analytical skills, creative thinking, and self-motivation. - Capability to work in a cross-functional, multi-site team environment. - Previous experience in DRAM/NAND layout design is desirable. - Passion for attracting, hiring, and retaining engineers with an innovative mindset. - Collaboration skills with overseas teams to define and execute strategies across the organization. - Accountability for the technical solutions implemented by your team. Education requirements for this role include a BE or MTech in Electronic/VLSI Engineering. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming information usage for the betterment of all. Through a focus on technology leadership and operational excellence, Micron delivers high-performance memory and storage products that drive advancements in artificial intelligence and 5G applications. For more information about Micron Technology, Inc., please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant labor laws, regulations, and international standards.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Experience or strong interest in developing memory compilers, addressing layout-related issues, and ensuring optimization. Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area. Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL. Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and deliveryExcellent communication skills and proactive at work. Excellent communication skills and proactive at work

Greetings from ChipSmart! We are currently seeking Analog Layout Engineers with a minimum of 3 years of experience to join our team. The ideal candidate will be responsible for designing and implementing analog layout solutions for various semiconductor products. As an Analog Layout Engineer, you will collaborate with the design and verification teams to ensure the successful delivery of high-quality layouts that meet project requirements. Additionally, you will be involved in ensuring layouts comply with industry standards and best practices. Key Responsibilities: - Develop analog layout designs for semiconductor products - Collaborate with design and verification teams to meet project goals - Ensure layouts adhere to industry standards and best practices - Perform layout verification and debugging - Contribute to design reviews and provide input for design improvements - Work on multiple projects simultaneously and prioritize tasks effectively Qualifications: - Bachelor's degree in Electrical Engineering or related field - Minimum of 3 years of experience in analog layout design - Proficiency in layout tools and design methodologies - Strong understanding of semiconductor fabrication processes - Excellent problem-solving skills and attention to detail - Good communication and teamwork abilities If you are a motivated Analog Layout Engineer with a passion for semiconductor design and a desire to work in a dynamic team environment, we encourage you to apply for this exciting opportunity at ChipSmart. Join us in shaping the future of semiconductor technology!,

Education Graduation in Pharmacy Long Description The person should have knowledge in Manufacturing equipments. He should have exposure in equipment’s such as FBE,Fette/KORSCH M/C & auto coater M/C He should be able to handle equipment trouble shoot in Manufacturing department. He should have exposure in regulatory organization . He must have faced the USFDA ,MHRA & other regulatory audits. He should have the exposure in Caliber QAMS, elog, track wise ,SAP ,WIND ,CDAS & other software. He should have the exposure in process simplification/optimization ,SABA ,elog & SCADA. Competencies Work Experience 3-6 years work experience in Fette compression machine

We are hiring an experienced Analog Layout Engineer to join a high-performance team working on advanced node technologies. This is a great opportunity to work with a global leader in semiconductor technology. Location: Bangalore Experience: 8 10 Years Employment Type: [Contract] Key Responsibilities: Handle block-level and top-level analog layout. Work on matching techniques, layout parasitics, and advanced layout methodologies. Work independently and collaboratively in a cross-functional team. Ensure quality layout delivery meeting DRC, LVS, and reliability checks. Required Skills: Solid understanding of analog layout fundamentals and design methodologies. Proficiency in 28nm, 22nm, and 16ff technology nodes. Strong experience with Cadence tools (Virtuoso, Assura, Calibre, etc.). Good team player with excellent communication skills.

As an Analog Layout Engineer at Power Soc, a leading innovator in the semiconductor industry, you will be responsible for designing and laying out analog and mixed-signal integrated circuits (ICs) using industry-standard CAD tools. Your role will involve collaborating with circuit design engineers to understand design specifications, performing layout verification, and optimizing layouts for performance, area, and manufacturability. Additionally, you will participate in design reviews, work closely with process engineers to ensure layout compatibility with fabrication processes, and mentor junior layout engineers. To excel in this role, you should have a Bachelor's or Master's degree in electrical engineering, electronics, or a related field, along with 5 to 12+ years of experience in analog/mixed-signal IC layout. Proficiency in CAD tools such as Cadence Virtuoso, Mentor Graphics, or similar is essential. A strong understanding of semiconductor device physics and fabrication processes, as well as experience with layout techniques for high-performance analog circuits, including matching, shielding, and noise reduction, are also required. Knowledge of ESD and latch-up prevention techniques, excellent problem-solving skills, attention to detail, and strong communication and teamwork skills will be beneficial in this role. Preferred qualifications for this position include experience with advanced process nodes, familiarity with RF layout techniques, and experience in tape-out and post-layout verification. Power Soc offers a competitive salary, performance-based bonuses, comprehensive health, dental, and vision insurance, a retirement savings plan with company match, opportunities for professional development and career growth, as well as flexible work hours and remote work options. Join our dynamic team at Power Soc and contribute to developing cutting-edge technology solutions in the semiconductor industry.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelors or master’s in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools – Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages – , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Roles and Responsibilities Work closely with CAD and custom macro/memory design leads to understand the design methodology and high level requirements and develop flows. Develop efficient analysis and model generation methodologies for timing and noise to achieve tight correlation. Determine key areas where automation and leading methodologies can help improve PPA. Define, innovate and implement new infrastructure capabilities that can be used to accelerate design and development, and improve user experience. Preferred qualifications MS degree in Computer Engineering; 5+ years of practical experience Strong skills in transistor level signoff tools for timing, emir, simulations, extraction and IPQA. Experience in flow development at high scale (multithreading, ml capabilities, hyperscaling, schedulers, filer hot-spot management etc.). Direct experience with efficient visualization tools to analyze results, log parsers, web views, error/warning scanners etc. Strong fundamentals in scripting languages (python, tcl, sh. others), automation, general purpose CAD infrastructure and flows. Good understanding of stdcell or memory design fundamentals. Excellent partner collaborating with design team in flow debug and support. Experience with signing off accuracy and correlation of analysis flows (compare to spice, foundry models, etc.) Tool knowledge in any of these is a plus – nanotime, xa/spectre, liberate, primelib, totem

We are seeking a highly skilled and motivated Analog Layout Leader to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore Work Expertise : 5 Years 12 Years DESIRED PROFILE : Expertise in working with large analog layout teams Expertise working on high-performance cores Expertise in working on planar and finfet technology nodes Expertise in executing the mixed signal layout, lvs / drc /antenna checks on complex custom analog/RF mixed-signal integrated circuits. Expertise in working with circuit designers and CAD engineers to perform custom analog mixed signal blocks layout Expertise in custom layout design techniques, CAD methodologies and process flows Expertise in Transistor level floorplan in a multi-voltage, mixed-signal, high speed and noise-sensitive environment Expertise in analog layout techniques like Device matching, shielding, LOD/STI, WPE, PSE, OSE, RF Concepts, minimizing parasitics and highpower routing JOB SPECS : Responsible to perform IC mask layout design and physical verification of Custom analog / RF mixed signal, IO & ESD designs and Block/Module level Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire, build technical teams from scratch and manage high caliber technical teams across GCC, ODC and onsite. Must be willing to work at customer sites as per customer needs Must be willing to travel worldwide at short notice as per customer needs Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

About Tessolve: Tessolve offers a unique combination of design, test, and product engineering services, enabling our customers to bring products from concept to high-volume production. With a strong presence in semiconductor engineering, we provide a robust environment for growth, learning, and career development. Job Description: We are looking for a skilled and motivated Analog Layout Engineer with 1 3 years of experience in deep sub-micron analog/mixed-signal layout design. The ideal candidate will be responsible for implementing transistor-level layout of analog and mixed-signal blocks while ensuring best practices in layout techniques for matching, parasitic reduction, and reliability. Job Title: Analog Layout Engineer Experience: 1 to 3 Years Location: Bangalore Key Responsibilities: Ownership of full-custom analog layout blocks from schematics to verified layout. Work closely with circuit design engineers to understand requirements and deliver robust layouts. Perform layout verification using DRC, LVS, ERC, and PEX tools. Support block-level and top-level integration. Optimize layout for performance, area, power, and reliability across different PDKs (90nm, 65nm, 28nm, etc.). Deliver high-quality GDSII on schedule. Required Skills & Experience: 1 to 3 years of hands-on experience in analog layout design . Strong understanding of analog design fundamentals and layout techniques (matching, shielding, symmetry, etc.). Experience in Cadence Virtuoso layout tools and verification tools like Calibre or Assura. Good knowledge of CMOS process and parasitic effects . Exposure to layout of blocks such as op-amps, bandgap references, data converters, PLLs, LDOs, etc., is a plus. Strong communication skills and ability to work collaboratively in a team environment. Preferred Qualifications: Bachelor s/Master s degree in Electronics, ECE, VLSI, or related discipline . Understanding of ESD/Latch-up rules and reliability best practices. Experience in scripting (SKILL, Python) is a plus.

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Lead layout design activity and work with design team. Produce high quality IPs/AMS Blocks/Macros. Drive Area estimation, floor planning, placement, routing, power planning, verification, EMIR, ESD-LUP verification and tape out activity. Mentor Junior Analog IC Layout engineers. Develop scripts. You will be reporting to Director -Layout Design What youll need: Minimum 6 years of experience in Analog Layout. Minimum Education requirement is bachelors degree in electrical engineering. Understanding of low parasitic, high frequency design techniques. Excellent understanding of analog layout concepts and issues. Experience in handling blocks and macros layout towards successful, high-quality, and execution Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry. Experience with multiple foundries in lower node eg: Samsung, TSMC, GF. Experience with Cadence tools (Virtuoso), Synopsys (CC), Calibre and ICV verification tools like LVS, DRC, Extraction etc. Experience with EMIR, PERC tools. Skill/TCL scripting experience. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

Roles and Responsibility 3+ years to 10 yrs design experience Experience with owning chip level DFT and Post Silicon debug / analysis Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. Preferred Skills/ Experience Experience with TCL / Perl is preferred. Understanding of IC design with Analog circuits and it s design cycles is an added advantage. Effective communication skills to interact with all stakeholders. Team and People Skills: The candidate should have good people skills to work closely with the systems, analog, layout and test team Must be highly focused and remain committed to obtaining closure on project goals

Lead and manage the analog and RF layout team for high-performance semiconductor products Oversee layout planning, floorplanning, and routing for RF, analog, and mixed-signal IC designs. Work closely with circuit design teams to optimize layouts for performance, area, and manufacturability. Ensure DFM (Design for Manufacturability), DRC (Design Rule Check), LVS (Layout vs. Schematic), and EM (Electromigration) compliance. Drive automation and layout methodologies to improve efficiency and quality. Collaborate with foundry partners for process design kits (PDKs), layout guidelines, and tape-out requirements. Provide technical mentorship to layout engineers and review critical blocks. Own full-chip layout integration and support post-layout simulations. Qualifications: 8+ years of experience in analog/mixed-signal/RF IC layout. Strong expertise in FinFET (e.g., 16nm, 7nm, 5nm) or advanced CMOS nodes. Hands-on experience with Cadence Virtuoso, Calibre DRC/LVS, and Mentor Graphics tools. Knowledge of high-frequency layout techniques, parasitic-aware layout design, and shielding strategies. Experience in power management, high-speed SerDes, RF front-ends, or ADC/DAC layouts is a plus. Proven ability to lead teams, review layouts, and drive tape-out schedules. Strong understanding of wafer-level packaging and chip integration. Excellent problem-solving and communication skills.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus.

Responsible for Memory Compiler layout development and verification. Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work. Contribute to effective project-management. Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.

Job Specs : We are seeking a highly skilled and motivated Analog Circuit Designer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of Analog / Mixed Signal IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C with 4+ Years of work expertise in mixed-signal or CMOS circuit design Expertise in analog blocks like power management DC-DC convertor, LDOs or Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells Design and architect CMOS analog and mixed-signal integrated circuits Simulate designs with state-of-the-art CAD tools Document designs and simulation results Experience with high-speed SERDES circuits Knowledge of layout issues Experience with circuit simulators (HSPICE, Spectre, etc) Experience with Cadence Design Environment is an asset Working knowledge of PERL and UNIX shell scripting languages is an asset Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only Location : Moscow, USA,Bengaluru,Hubli,Kolkata

Description: Description: Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 5 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm & 5+ exp **** TSMC Certification?Additional Details Target Rate : 0.00TSMC Certification? : YesShift : IND|1DAYH : Mon to Fri - 8 Hours - 9am to 6pmAccess Type : Account with Email

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: Analog Layout. Experience3-5 Years.