267 Analog Layout Jobs - Page 2

Design and optimize analog and digital circuit layouts. Ensure layout designs meet all design specifications and industry standards. Collaborate with cross-functional teams including circuit designers and verification engineers. Required Candidate profile Knowledge of CMOS, BiCMOS, and bipolar technologies. Experience with EDA tools such as Cadence Virtuoso and Mentor Graphics. Ability to work collaboratively in a team environment. Perks and benefits Employee discounts, free meals, or snacks.

Must have 3-5 of experience in standard cell layout, analog, mixed-signal and custom digital block designs in advanced CMOS process. Should have expertise in multiple standard cell layout library developments. Should be able to perform standard

i)Analog Layout Engineer Skills: who worked on Lower nodes 3nm, 5 nm, 7 nm, 10 nm Exp: 4-9yrs Loc: HYD ii) Skills: Non intel Exp Exp:6+yrs Loc: BLR iii)Skills: finfet nodes Exp:8+yrs Loc: BLR

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

General Summary: Posting Title: Analog/Mixed Signal PLL Analog Designers Bangalore (BDC), India Job Function Qualcomm Mixed-Signal IP team is actively seeking for analog circuit designers (3-10yrs) to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC and the integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products in leading-nodes - finfets & beyond. Design goals include low-power & low voltage analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Architecture, design, and development ...

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. - Hold a D...

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate ...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: 2026 Campus Hire_ Engineer_ HW Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into model...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple f...

Responsible for Design and development of critical analog, mixed-signal, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time de

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

As a Senior Layout Engineer at SILCOSYS Solutions, you will play a crucial role in designing and verifying analog circuit layouts. You will collaborate with circuit design teams, perform physical verification, and ensure compliance with industry standards. Your day-to-day tasks will involve layout design of analog circuits, circuit design collaborations, conducting design reviews, and resolving layout-related issues. Key Responsibilities - Design and verify analog circuit layouts - Collaborate with circuit design teams - Perform physical verification tasks - Ensure compliance with industry standards - Conduct design reviews - Resolve layout-related issues Qualifications - Experience in Layou...

We’re hiring Analog Layout Engineers (3–7 years) with hands-on experience in lower technology nodes, layout design, and DRC/LVS verification. Location: Hyderabad. Immediate joiners preferred.

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shi...

Designation: Principal AMS Layout Leader (Global Product Solution Opportunity) Exp Range: 15-25 Yrs Location: Hyderabad Job Description A layout technical expert taking chip top ownership of analog-on-top ASIC developments. Hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders. Required experience: 15+ years of experience Experience with nodes in the range of 22nm-40nm-180nm is a must. Experience with BCD technologies is a must. Proven track record of owning chip top layout. Must be able to independently go through required tape-out procedures and take corre...

Responsibilities: Must have solid understanding of analog & mixed signal design fundamentals Design of basic analog IPs like LDOs, DC-DC converters, ADC/DACs, PLLs,Oscillators, Temperature sensors, Bandgap references and voltage monitors. Circuit design implementation of SERDES blocks like Transmitter, CTLE, SAL,DLL, Phase Interpolator, DFE and FFE Working Experience in Die to Die interconnect high speed IO designs, HBM, DDRand UCIe protocols. Hands on experience on lower FINFET technology nodes Basic analog layout knowledge especially with FINFET technology Expertise in following tools and standards: Cadence and Synopsys mixed signal design tool flow Requirements: The Candidate should have ...

Role Overview: You will be responsible for executing internal projects or small tasks of customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. As an individual contributor, you will work on tasks such as RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, Signoff, etc. Your primary goal will be to complete the assigned tasks successfully on time with minimal support from senior engineers while ensuring quality delivery as approved by the senior engineer or project lead. Key Responsibilities: - Work on any one task of RTL Design/Module in Verification/PD/DFT/Circuit Design/Analog L...

Role : (in 100 to 150 words) Participate in consulting assignments, identify and mentor Six Sigma and Lean projects, and drive process improvement activities and business transformation in the customer service vertical. Reports into : (RM Designation) GM QPE Job Responsibilities : (Must have) (min 8 pointers & max 12) Participate in PEx. consulting assignments Identify and mentor Six Sigma and Lean projects Conduct Value Stream Mapping/Process Mapping Ensure compliance with ISO 9001/ 27001 standards Drive process improvement activities Lead business transformation initiatives Promote and drive the Six Sigma culture and initiatives Mentor MBB , BB , Green Belt trainees Recommend new/improveme...

Job Description A layout technical expert taking chip top ownership of analog-on-top ASIC developments. Hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders. Required experience: 15+ years of experience in custom analog layout Experience with nodes in the range of 22nm-40nm-180nm is a must. Experience with BCD technologies is a must. Proven track record of owning chip top layout. Must be able to independently go through required tape-out procedures and take corrective actions. Must be able to take ownership of internal layout flows, continuously work on imp...

As a High-Speed Analog Layout Engineer at our company, you will be responsible for designing high-speed analog and mixed-signal layouts, focusing on advanced FinFET nodes such as TSMC 2nm, 3nm, 5nm, and 7nm. Your role will require you to have a strong background in custom layout for high-speed IPs like PLLs, SERDES, clock buffers, and data paths. Key Responsibilities: - Hands-on experience in custom layout for high-speed IPs including PLLs, SERDES, clock buffers, and data paths - Proficiency in tools like Cadence Virtuoso, Calibre DRC/LVS, and PEX flows - Demonstrated track record of delivering clean layouts with successful DRC/LVS/EM/IR sign-offs through multiple tapeouts - Expertise in lay...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

Responsibilities: Assist in RTL design, verification, or physical design Projects. Work with teams on ASIC/FPGA/SoC design flow and related activities. Learn and use EDA tools for simulation, synthesis, and timing analysis. Support in testbench development, debugging, and documentation. Stay updated on latest semiconductor technologies. Required Skills: Strong understanding of Digital Electronics and CMOS fundamentals. Knowledge of Verilog / VHDL / SystemVerilog. Familiarity with C / C++ / Python scripting is an advantage. Basic exposure to EDA tools preferred. Good problem-solving and analytical ability.