Lead ASIC Digital Design Verification (Full Chip & IP Verification) Synopsys

4.0 - 8.0 years

4 - 8 Lacs

Bhubaneswar, Odisha, India

On-site

What You ll Be Doing: Leading the digital verification flow for PVT Sensor Digital Verification. Setting up and managing AMS Verification and front-end Integration for MSIPs. Developing and supporting next-generation analog, digital, and mixed-signal IPs. Ensuring all blocks are verified for behavioral and functionality from top-level integration. Collaborating with a team to intercept TQV and other swim lanes for top-level integrations. Implementing mixed-mode simulations with significant improvements in execution time. The Impact You Will Have: Enhancing the reliability and performance of semiconductor lifecycle management solutions. Accelerating the integration of intelligent in-chip sens...

Posted 3 months ago

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Analog Modeling,Verification and characterization Senior Lead Engineer Qualcomm

3.0 - 8.0 years

3 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing an...

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AMS Verification Kaizen SRA Technologies Private Limited

6.0 - 15.0 years

4 - 14 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

Job Role : AMS Verification Experience range : 6-15 Yrs Location : Hyderabad Availability : Immediate 30 days Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench dev...

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