12 Ams Verification Jobs

Role: AMS Verification Engineer / Sr. Engineer Experience required: 5-15 years Work location: Pune, Bangalore, Hyderabad, Chennai, and Noida Minimum 5 Years of overall experience in ASIC Verification Should have worked on AMS Verification for a minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools such as Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Cadence Virtuoso, Spectre, or AMS Designer.

What You ll Be Doing: Leading the digital verification flow for PVT Sensor Digital Verification. Setting up and managing AMS Verification and front-end Integration for MSIPs. Developing and supporting next-generation analog, digital, and mixed-signal IPs. Ensuring all blocks are verified for behavioral and functionality from top-level integration. Collaborating with a team to intercept TQV and other swim lanes for top-level integrations. Implementing mixed-mode simulations with significant improvements in execution time. The Impact You Will Have: Enhancing the reliability and performance of semiconductor lifecycle management solutions. Accelerating the integration of intelligent in-chip sensors and analytics capabilities. Optimizing performance, power, area, schedule, and yield for cutting-edge technology products. Reducing risk and time-to-market for differentiated products. Contributing to the development of Synopsys next-generation analog, digital, and mixed-signal IPs. Supporting the growth and success of Synopsys Sensor IP business unit. What You ll Need: BS or MS degree in Electrical Engineering, Computer Science, or Computer Engineering. 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development. Expertise in Digital Verification and/or AMS Verification with Verilog A and RNM. Proficiency in System Verilog and RNM (Real Number Modeling). Understanding of latest foundry PDKs and their usage in FE & BE flows. Who You Are: A detail-oriented and highly motivated verification engineer. A collaborative team player with excellent communication skills. A continuous learner eager to stay updated with industry trends and technologies. A leader capable of guiding and mentoring teams to achieve verification goals. A problem-solver with strong analytical and debugging skills. The Team You ll Be A Part Of: You will be a key member of Synopsys rapidly expanding Sensor IP business unit, working with a team of experts dedicated to developing and verifying next-generation analog, digital, and mixed-signal IPs. The team focuses on integrating intelligent in-chip sensors and analytics capabilities to enhance semiconductor lifecycle management solutions. Together, you will contribute to the success of Synopsys innovative technology products, driving the future of the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim. Create Liberty (.lib) timing and power models and validate them against transistor-level designs. Develop and maintain self-checking testbenches and test plans for model verification. Conduct functional analysis and verification of modeled IPs using simulators like VCS. Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices. Automate model generation and verification workflows using Tcl, Perl, or Skill scripting. Interface with design and verification teams to ensure model accuracy and completeness. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field and 3+ years of relevant hardware modeling experience OR Master's degree and 2+ years of experience OR PhD and 1+ year of experience. Required Skills & Experience: 5+ years of experience with timing/power characterization and view generation tools (e.g., Silicon Smart, HSPICE, FineSim). Strong understanding of mixed-signal analog IP design and functionality. Expertise in Verilog and Verilog-AMS behavioral modeling. Hands-on experience with simulation and verification tools such as VCS. Experience with Liberty file format and creating timing/power views. Knowledge of AMS verification environments is a plus. Strong scripting skills in Tcl, Perl, and/or Skill for automation. Excellent problem-solving, collaboration, and communication skills.

Job Role : AMS Verification Experience range : 6-15 Yrs Location : Hyderabad Availability : Immediate 30 days Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOC's or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage

Role & responsibilities : Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Preferred candidate profile Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Experience Level 7+ years

Description: Job Title: Memory Circuit Design Verification Engineer Memory Circuit Design Verification Engineer Description As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. Responsibilities Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Experience Level 3-7+ years Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

Role & responsibilities Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work with international colleagues on developing new verification flows to take on the challenges in design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Core Requirements Good communication skills and ability to work well in a team Guide new team members and energetic engineers in the team Analytical capability for complex CMOS and/or gate level circuit designs Proficient with either SPICE and/or Verilog simulations Qualifications & Skills Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Preferred candidate profile Immediate to Max 15 Days Joiner Perks and benefits

As a AMS Verification Engineer one should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Job Description In your new role you will: Ability to lead MSV and/or DV verifications. Involved in verification for IPs . Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer. Test plan preparation as per the dynamics of product specifications. Behavioral modeling: Verilog, real or SV-RNM . Dealing challenges with AMS methodologies of Cadence : irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS. Testcase Debug & proposing new scenarios. Ability to strategize optimization of simulation bench for simulation time. Your Profile You are best equipped for this task if you have: Bachelors with 9+ years or Masters with 8+ years of experience. Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage. HDL/HVL : Verilog / Verilog-ams , SV/UVM added advantage. Tools: Cadence Xcelium spectre / Synopsys XA-VCS / Mentor Eldo ADMS . Automation: Perl/python/shell. Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements. Ability to drive projects and debug independently.

Experience range from 4+ years. Hands-on experience Verilog-AMS, System Verilog, and UVM methodologies. Experience with Cadence Spectre or similar AMS simulation tools, Strong understanding of analog circuit design principles (op-amps, transistors, etc.)

Dear Applicants We, Cyient is hiring for Technical Specialist: Analog Mixed Signal Verification for End to End Offshore-Onshore Model based Global Product R&D from scratch-based Opportunity. Base Location: Bangalore, Pune & Hyderabad Experience Range: 2-12 Yrs Key Skills: Have at least 2yrs experience in AMS verification Have sound knowledge of AMS verification flow Have sound knowledge of different modeling techniques (WREAL/electrical/SV RNM) Have experience in PMIC blocks (like Buck, Boost and LDO) AMS verification Have basic understanding of SV UVM Be good in basic Analog, Digital and AMS concepts Be good in oral and written communication Interested AMS Verification Specialists, kindly share updated CV to rajanikant.sharma@cyient.com for detailed discussion. Thanks and Regards Rajani Kant Sharma Sr Recruiter: Global Lateral Hiring: Semicon Vertical Cyient

Role & responsibilities Guide and set the direction for the AMS/Co-Sim verification effort for the HBM program. Build the AMS/Co-Sim simulation plan and environment for all upcoming HBM designs. Simulate, analyze, and debug pre-silicon block level IPs and full chip designs. Develop test cases/stimulus to increase the functional coverage. Drive mixed signal verification methodology in collaboration with the global HBM team Preferred candidate profile Experience in AMS verification and co-sim History of driving AMS/Co-Sim verification methodology, tool bring-up, and mentoring teams Good to have experience in working with design analog and custom logic schematics Good to have understanding of PLL, LDO, charge pumps and any other analog IP's Good to have experience in DRAM, SRAM, other memory related fields or any custom design Good to have experience in analog-digital co-simulations Good to have experience in SystemVerilog/UVM