22 Ams Verification Jobs

Job Description: SchipSemi is the pioneering IT/semiconductor company located in Muzaffarpur, Bihar. We are dedicated to translating product visions into tangible designs with the help of engineering expertise and ecosystem partnerships. Our primary focus lies in aiding companies in setting themselves apart, transforming business functions, and expediting revenue growth. We are currently seeking experienced VLSI Engineers to join our team on a full-time on-site basis at SchipSemi. The ideal candidates should possess a minimum of 3+ years of hands-on experience in the following specialized areas: 1. STA (Static Timing Analysis) 2. Formal Verification 3. Embedded Software Development 4. AMS (Analog and Mixed Signal) Verification We have immediate openings for the following positions: 1. STA Engineer with over 5 years of experience for a role based in Malaysia 2. Formal Verification Engineer with over 4 years of experience for a role based in Malaysia 3. Embedded Software Developer with over 3 years of experience for a role based in Malaysia 4. AMS Verification Engineer with over 4 years of experience for a role based in Bangalore Qualifications: - Strong analytical and problem-solving skills - Proficiency in semiconductor technologies - Familiarity with industry tools and software If you meet the above qualifications and are ready to join immediately, we encourage you to apply without delay. Please send your resumes to neeraj.rai@schipsemi.com and praveena.bandla@schipsemi.com at your earliest convenience. Don't miss out on this opportunity - apply now!,

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description In your new role you will: Candidate should have working experience with AMS Verification on multiple SOCs or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Your Profile You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer Partial Ability to drive MSV project independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

As a VLSI Engineer at SURESH CHIPS AND SEMICONDUCTOR (SchipSemi), the first IT/semiconductor company in Bihar state located in Muzaffarpur, your role will involve utilizing your expertise to transform product visions into real-world designs. SchipSemi specializes in engineering solutions and fostering ecosystem partnerships to help companies differentiate themselves, revamp business functions, and expedite revenue growth. This full-time on-site position requires VLSI Engineers with hands-on experience in the following areas: 1. STA 2. Formal Verification 3. Embedded Software Developers 4. AMS Verification We are currently seeking Engineers with the following expertise: 1. STA: 5+ years of experience for roles based in Malaysia 2. Formal Verification: 4+ years of experience for roles based in Malaysia 3. Embedded Software Developers: 3+ years of experience for roles based in Malaysia 4. AMS Verification: 4+ years of experience for roles based in Bangalore Qualifications: - Strong analytical and problem-solving skills - Experience with semiconductor technologies - Knowledge of industry tools and software Immediate joiners are preferred due to urgency in hiring. If you meet the qualifications and are ready to take on challenging projects in the semiconductor industry, we encourage you to apply promptly. Please send your resumes to neeraj.rai@schipsemi.com and praveena.bandla@schipsemi.com. Apply now and be a part of our dynamic team at SchipSemi.,

As a Senior Circuit Design Verification Engineer at Micron Technology, you will be part of a highly innovative and dynamic team working with cutting-edge memory technologies. Your primary responsibility will be to lead the verification effort to ensure the accurate and timely delivery of sophisticated memory designs. You will have the opportunity to work on full chip gate level custom designs with advanced low power and power management technologies, covering categories such as DDR4, LPDDR4, DDR5, and LPDDR5, operating at high speeds of up to 6400MT/s. In this role, you will collaborate closely with global design and verification team members, leveraging their extensive experience in memory design. Your responsibilities will include guiding the verification effort, providing support to design projects by simulating and analyzing designs, developing test cases to increase functional coverage, and participating in the development of verification methodology and environments for complex products. Additionally, you will work on developing new verification flows and maintaining test benches using simulation tools. To succeed in this role, you should possess strong communication skills, the ability to work well in a team, and analytical capabilities for complex CMOS and gate level circuit designs. Proficiency in SPICE and/or Verilog simulations, as well as experience in SystemVerilog, PLI coding, UVM Test Bench, DRAM, SRAM, and AMS verification, are essential qualifications for this position. A Bachelor's or Post Graduate Degree in Electronics Engineering or a related field is required. Micron Technology is a global leader in memory and storage solutions, driving innovations that transform how information enriches lives worldwide. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. By joining Micron, you will be part of a team that fuels the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. To learn more about Micron Technology and explore career opportunities, please visit micron.com/careers. For assistance with the application process or to request accommodations, please contact hrsupport_in@micron.com. Micron Technology complies with labor laws and standards, prohibiting the use of child labor and ensuring adherence to applicable regulations.,

You will work in the AMS Verification domain, requiring relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is considered a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools is essential. You should have knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles. Analog circuit basics understanding is necessary, and previous analog design experience would be a plus. You should be familiar with the concepts of behavioral modeling, including digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from a mixed signal perspective is advantageous. Functional knowledge of analog and mixed signal building blocks such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Previous experience working on AMS Verification on multiple SOCs or sub-systems is required. Working knowledge of Perl/Skill/Python/Tcl or other scripting relevant languages would be beneficial. You must possess the ability to lead a project team and work collaboratively in a multi-site development environment. Being delivery-oriented, passionate to learn and explore, transparent in communication, and flexible related to project situations is important. A good knowledge of analog and mixed signal electronics, test-plan development, tools, and flows is necessary. You will be responsible for developing and executing top-level test cases, self-checking test benches, and regression suites. Additionally, you will develop and validate high-performance behavior models and verify block-level and chip-level functionality and performance. Being a team player with good communication skills and having previous experience in delivering solutions for a multi-national client is valuable. You should be fluent with Cadence-based flow, creating schematics, Simulator/Netlist options, etc. Ability to extract simulation results, capture them in a document, and present them to the team for peer review is required. Supporting silicon evaluation and comparing measurement results with simulations is part of the role. Having UVM and assertion knowledge would be an advantage.,

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,

The position of AMS Verification Lead Led Model is currently open in Bangalore with 1+5 positions available. We are looking for individuals with 2 to 12+ years of experience in this field. Key Responsibilities: - Developing and executing AMS verification plans for mixed-signal IP and SoCs. - Creating and validating behavioral models using Verilog-A for analog and mixed-signal blocks. - Implementing and optimizing AMS testbenches in the Xcelium simulation environment. - Collaborating with analog and digital designers to verify top-level integration and system performance. - Debugging and resolving complex AMS simulation and modeling issues. - Driving and contributing to the development of AMS verification methodologies and best practices. - Performing regression testing and coverage analysis to ensure design robustness. - Documenting verification plans, results, and technical reports. If you are interested in this position, please share your resume to jayalakshmi.r2@ust.com. Feel free to share any references you may have. Regards, Jaya,

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

8+ yrs of experience in AMS verification and mixed-signal design, UVM System Verilog (UVM/SV), and C-based compile flow, ARM M-series (Cortex M33, M85, M55, M4, M0 etc) and RISC-V processor, Spectre and Xcelium tools, scripting - Python, Perl

This is a full-time on-site role for an AMS Verification Engineer at UANDWE, Inc. in Bengaluru. As an AMS Verification Engineer, you will have complete ownership of AMS verification for complex mixed signal blocks such as PLL, DFE, transmitters, receivers, etc. It is essential for you to understand the JDEC spec for DDR interface and define verification methodology. Your responsibilities will include test planning, creating testbenches, and verification using Cadence tool mixed signal design flow. Knowledge of RNM (real number model) modelling would be a plus. You will collaborate closely with Logic and Analog design teams to comprehend the requirements and provide feedback on the results. Additionally, you will be responsible for creating schedules, tracking progress, and identifying and addressing issues and risks to project management. To qualify for this role, you should hold a Masters or Bachelor's degree in Electronics Engineering, VLSI, or Microelectronics from a reputed university. You should have a minimum of 7 years of industry experience in AMS verification. Strong written and verbal communication skills are required, as well as the ability to work effectively as a team player with cross-functional teams.,

Key Responsibilities Architect and implement System Verilog/UVM-based testbenches and verification environments for analogmixed signal blocks and SoCs. Develop VerilogA , RealNumber Models (RNM) , WREAL models, and support cosimulation with SPICE for behavioral accuracy. Execute verification of highspeed serial protocols including PCIe , USB 3 , MIPI CSI/DSI , using constrainedrandom stimulus, assertions, monitors, functional coverage. Utilize tools like PrimeSim XA (VCS AMS) to run mixed-signal regressions and VerilogA analog simulations. Collaborate closely with digital, analog, synthesis, timing, and silicon bring-up teams to ensure spec traceability, debug failures, and validate first-pass silicon performance. Write thorough verification plans , track coverage closure, debug RTL/AMS models, document results, and drive continuous improvement of methodologies. Qualifications & Skills Bachelors/Masters in Electronics/Telecommunication, Computers, Electrical . 5+ years of mixed-signal/AMS verification experience; SoC-level IP/subsystem/SoC verification preferred. Deep proficiency in System Verilog , UVM , assertions, functional coverage, OOP testbench design. Strong expertise in VerilogA , RNM/WREAL , and building analog behavioral models Simply. Hands-on experience with PrimeSim XA/VCS AMS , Cadence Spectre/Xcelium, Synopsys AMS toolchains.

Key Responsibilities: Lead full-cycle Analog IP Development from circuit design to layout, AMS verification, and characterization. Hands-on experience in designing LDOs, Band Gap References, Current Generators, POR, ADC/DACs, PLLs, Oscillators, IOs, Temperature Sensors, SERDES, PHYs, High-Speed IOs, and more. Design & layout expertise in advanced CMOS and lower FINFET nodes. Strong grasp of design constraints, layout quality, and PPA trade-offs. Experience conceptualizing and implementing chip-level mixed signal simulations (testbenches, scripts, etc) Ownership of characterization and post-silicon validationAbility to lead teams and drive high-quality execution across subsystems

Role & responsibilities Job Description Must have: Lead the verification of analog and mixed-signal IPs such as bandgaps, LDOs, multi-phase buck regulators, comparators, and functional safety (FuSa) monitoring circuits. Own and execute comprehensive verification plans for assigned blocks or features, ensuring complete coverage and robust test quality. Develop or enhance analog behavioral models using System Verilog Real Number Modelling (SV-RNM). Validate digital functionalities including CRC checks, clock monitors, register maps, OTPs, and communication interfaces. Apply strong SystemVerilog skills, including the use of assertions and cover groups. Utilize advanced debugging techniques across RTL and schematic views at the top level. Manage and maintain VSIF files to support verification regression workflows. Conduct coverage analysis using tools such as IMC or vManager. Write or maintain automation scripts (Make files preferred) to streamline verification processes. Work independently with minimal supervision, managing tasks and priorities effectively. AMD (Dont Share AMD Profiles) Preferred candidate profile

We're looking for a highly experienced and influential Senior Mixed-Signal Design Verification Engineer to join our dynamic team. As a key member of our design verification group, which includes both mixed-signal and digital verification engineers, you'll be responsible for formulating comprehensive verification strategies and leading, driving, and completing the verification of large, integrated products. As a senior contributor, you'll be expected to lead and influence verification methodologies within both your business unit and across Analog Devices. We also encourage active participation in cross-company technical initiatives, as well as patenting and publishing your work when possible. Requirements: B.Tech / M.Tech with 5+ years of industry experience in analog/mixed-signal behavioral modeling at various levels of abstraction, and full-chip verification (AMS and DMS DV). Strong understanding of analog design concepts and mixed-signal design architectures. Exposure to products that integrate a wide variety of analog functions.

Key Responsibilities: Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools like Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications.

Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful: Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have: Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What Makes You Eligible: An accomplished leader with a minimum of 8+ years of experience in software design & development and a Bachelor's / Master's degree Excellent communication skills (written/verbal) & team spirit Risk taker with passion for innovation Autonomous working to explore new technologies

Role: AMS Verification Engineer / Sr. Engineer Experience required: 5-15 years Work location: Pune, Bangalore, Hyderabad, Chennai, and Noida Minimum 5 Years of overall experience in ASIC Verification Should have worked on AMS Verification for a minimum of 2 years Develop and execute verification plans for AMS designs. Create test benches and run simulations using tools such as Cadence Virtuoso, Spectre, or AMS Designer. Verify mixed-signal blocks (e.g., ADCs, DACs, PLLs) and ensure proper analog-digital interaction. Debug and resolve design issues in collaboration with design teams. Document verification results and ensure compliance with design specifications. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Cadence Virtuoso, Spectre, or AMS Designer.

What You ll Be Doing: Leading the digital verification flow for PVT Sensor Digital Verification. Setting up and managing AMS Verification and front-end Integration for MSIPs. Developing and supporting next-generation analog, digital, and mixed-signal IPs. Ensuring all blocks are verified for behavioral and functionality from top-level integration. Collaborating with a team to intercept TQV and other swim lanes for top-level integrations. Implementing mixed-mode simulations with significant improvements in execution time. The Impact You Will Have: Enhancing the reliability and performance of semiconductor lifecycle management solutions. Accelerating the integration of intelligent in-chip sensors and analytics capabilities. Optimizing performance, power, area, schedule, and yield for cutting-edge technology products. Reducing risk and time-to-market for differentiated products. Contributing to the development of Synopsys next-generation analog, digital, and mixed-signal IPs. Supporting the growth and success of Synopsys Sensor IP business unit. What You ll Need: BS or MS degree in Electrical Engineering, Computer Science, or Computer Engineering. 4-8 years of experience in design and verification for leading-edge Digital SOC chip design and IP development. Expertise in Digital Verification and/or AMS Verification with Verilog A and RNM. Proficiency in System Verilog and RNM (Real Number Modeling). Understanding of latest foundry PDKs and their usage in FE & BE flows. Who You Are: A detail-oriented and highly motivated verification engineer. A collaborative team player with excellent communication skills. A continuous learner eager to stay updated with industry trends and technologies. A leader capable of guiding and mentoring teams to achieve verification goals. A problem-solver with strong analytical and debugging skills. The Team You ll Be A Part Of: You will be a key member of Synopsys rapidly expanding Sensor IP business unit, working with a team of experts dedicated to developing and verifying next-generation analog, digital, and mixed-signal IPs. The team focuses on integrating intelligent in-chip sensors and analytics capabilities to enhance semiconductor lifecycle management solutions. Together, you will contribute to the success of Synopsys innovative technology products, driving the future of the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim. Create Liberty (.lib) timing and power models and validate them against transistor-level designs. Develop and maintain self-checking testbenches and test plans for model verification. Conduct functional analysis and verification of modeled IPs using simulators like VCS. Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices. Automate model generation and verification workflows using Tcl, Perl, or Skill scripting. Interface with design and verification teams to ensure model accuracy and completeness. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field and 3+ years of relevant hardware modeling experience OR Master's degree and 2+ years of experience OR PhD and 1+ year of experience. Required Skills & Experience: 5+ years of experience with timing/power characterization and view generation tools (e.g., Silicon Smart, HSPICE, FineSim). Strong understanding of mixed-signal analog IP design and functionality. Expertise in Verilog and Verilog-AMS behavioral modeling. Hands-on experience with simulation and verification tools such as VCS. Experience with Liberty file format and creating timing/power views. Knowledge of AMS verification environments is a plus. Strong scripting skills in Tcl, Perl, and/or Skill for automation. Excellent problem-solving, collaboration, and communication skills.

Job Role : AMS Verification Experience range : 6-15 Yrs Location : Hyderabad Availability : Immediate 30 days Responsibilities: To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs. Leading a project for AMS requirements is a value add. Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS) Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected Experience working on AMS Verification on multiple SOC's or sub-systems Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations Candidates should have a good knowledge of analog and mixed signal electronics, test-plan development, tools and flows. Develop and execute top-level test cases, self-checking test benches and regressions suites Developing and validating high-performance behavior models Verifying of block-level and chip-level functionality and performance Team player with good communication skills and previous experience in delivering solutions for a multi-national client Tool suites : Predominantly analog (Cadence - Virtuoso). SPICE simulator experience Fluent with Cadence-based flow- Create schematics, Simulator/Netlist options etc. Ability to extract simulation results, capture in a document and present to the team for peer review Supporting silicon evaluation and comparing measurement results with simulations UVM and assertion knowledge would be an advantage