215 Amba Jobs - Page 5

Responsibilities: * Collaborate with cross-functional teams on design verification strategies * Develop UVM testbenches for SOCs using System Verilog and PCIe protocols

Lead Design Verification Engineer Bangalore We are looking for an experienced Lead Design Verification Engineer (412 yrs) to join our semiconductor team. Youll lead SoC/ASIC/IP verification using SystemVerilog, UVM, SVA, and drive test planning, coverage, regressions, and debug. ???? Must-have: Strong expertise in protocols (PCIe, DDR, USB, AMBA, MIPI, CXL), EDA tools (VCS, Xcelium, Questa), scripting (Python/Perl/Tcl), and low-power/CDC/formal verification. ???? Bonus: Experience with emulation/GLS, lint, DFT awareness, and leadership/mentoring. ???? Location: Bangalore, India ? Experience: 412 years ???? Apply now or share your profile at [HIDDEN TEXT] Show more Show less

What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. C...

You are a seasoned verification engineer with a passion for cutting-edge technology With a BSEE in Electrical Engineering and over 5 years of relevant experience, or an MSEE with over 4 years, you bring a wealth of knowledge in developing System Verilog based test environments, implementing test plans, and extracting verification metrics You possess strong HVL coding skills and hands-on experience with industry-standard simulators such as VCS, NC, or MTI, and waveform-based debugging tools Your familiarity with verification methodologies like VMM, OVM, or UVM is solid, and you have a deep understanding of protocols such as AMBA, SD/eMMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, and USB Your...

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu...

Hiring : ASIC Engineering Director : Experience : 20+Years Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it. KEY EXPERTISE : - Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP/Sub-...

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

We are seeking a highly experienced Staff Design Engineer with 10+ years of expertise in RTL design and digital signal processing for our Bengaluru location (max 30 days notice period). The ideal candidate will be responsible for designing, developing, and integrating custom DSP components such as filters, FFTs, and control logic for Aevas advanced 4-D Lidar processing chip across ASIC and FPGA platforms. The role involves creating micro-architecture specifications, writing and validating SystemVerilog RTL code, and ensuring designs meet stringent performance, low-power, and robustness requirements. The engineer will collaborate with architects, verification, and system software teams to ach...

1. Strong coding with Verilog and SystemVerilog 2. Good knowledge of AHB,AXI, AMBA protocol, exp in Ethernet 3. Many experiences with sequence creation, functional cover groups and assertion coding. 4. Strong C/C++ software development experiences 5. Be familiar with scripting language, such as Perl, C shell, Makefile, Ruby. Show more Show less

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and ...

Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. Wi...

You should have a strong understanding of Design & Verification methodologies related to either Times or Untimed SW Models, RTL IP, VIPs, and UVM Env. It is essential to be familiar with verification tools such as Simulator and Synthesis. Proficiency in C/C++, System Verilog, UVM, SystemC, and RTL is required. Knowledge of standard protocol interfaces like AMBA, Automotive, PCIe, and USB would be beneficial. Strong written and verbal communication skills are necessary, along with the ability to work effectively both independently and as part of a team. A self-motivated attitude and a collaborative approach to teamwork are also important attributes for this role.,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team in Bangalore/Hyderabad, India, contributing to cutting-edge technological work in the field of integrated circuits. Your expertise will be crucial in driving the design and verification efforts for complex IP/Subsystem/SoC blocks. Design Lead: In the role of RTL Design Lead, you will be responsible for ensuring bug-free RTL from requirements or specifications. Your experience in multiple tape-outs and driving the design effort for complex blocks will be instrumental in the success of our projects. Verification Lead: As a Verification Lead, your role will involve catching bugs and ...

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identify...

HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. With a strong foundation built on four decades of innovation, a world-renowned management philosophy, and a relentless focus on customer relationships, we pride ourselves on our culture of invention and risk-taking. HCL is committed to diversity, social responsibility, sustainability, and education initiatives, exemplified by our worldwide network of R&D facilities and co-innovation labs. With over 187,000+ Ideapreneurs across 50 countries, we deliver holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 ...

Position : ASIC Design Verification Engineer Requirements : 2Years to 15Years experience in SystemVerilog/UVM-based verification for IP/SoC Skills in assertions, formal verification and emulation Experience with high-speed interfaces (PCIe, DDR, Ethernet), scripting (Python, TCL, Perl) and working across cross-functional teams Responsibilities : Full verification closurefrom test planning and testbench development to formal, emulation-based verification and ensuring first-pass silicon success Role & responsibilities Preferred candidate profile

Core Technical Skills : SystemVerilog / UVM testbench and coverage methodologies Constraint-random verification, simulation and debug flow Formal verification techniques (e.g. Jasper, VC Formal) Scripting languages: Python, TCL, Perl, Shell Experience with high-speed protocols (PCIe, DDR, Ethernet) and emulation tools Resume & Interview Prep Advice : Highlight projects involving ASIC/SoC verification, testbench implementation, coverage closure using UVM/SystemVerilog Reddit+15Reddit+15Meta Careers+15Indeed+8Atos Jobs+8Indeed+8Reddit+1Indeed+1Reddit+2Meta Careers+2Reddit+2Reddit+2Reddit+2Reddit+2 Showcase contributions in debugging RTL, developing functional coverage models, and scripting aut...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Good knowledge on AMBA protocols (CHI/AXI/AHB) Knowledge of ARM architecture be an added advantage Exposure to low power methodology with understanding of UPF Execute verification plans, regression enabling for all features and, debug of the test failures Hands-on experience of GLS and timing simulations Exposure to Formal verification Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on e...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC desi...

As a Functional Verification Engineer at AMD in Hyderabad, you will be responsible for verifying the functionality of complex System on Chip (SOC) designs using industry-standard verification methodologies. With 4-10 years of experience, you will play a key role in ensuring the quality and reliability of ASIC designs. You should be proficient in UVM (Universal Verification Methodology) and have a strong command of Verilog or SystemVerilog. Additionally, knowledge of AMBA Bus Protocols is essential for this role. Your expertise in functional verification, design verification (DV), and ASIC verification will be crucial in meeting the verification goals of the projects. Working closely with cro...

Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, you enable customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, Siemens has quite a lot to offer. The company blurs the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow's idea. Siemens takes what the future promises tomorrow and makes it real for customers today. Join Siemens, where your car...

You are an experienced FPGA design engineer with over 3 years of experience, based in Vadodara, India. Your primary responsibility will be implementing control logic state machines and DSP algorithms in FPGA fabric for high throughput systems. You must possess excellent troubleshooting and debugging skills for both simulation and in-circuit scenarios. Your expertise should include continual integration of unit modules into FPGA top-level design, using SignalTap to debug logic and/or timing issues, constructing bypasses, data taps, and data pattern generators for isolation, managing timing closure and constraints files, and creating basic glue logic between DSP blocks. You should also be capa...