RTL Front end verification, IP Verification Engineer Acesoft Labs

3.0 - 8.0 years

5 - 10 Lacs

hyderabad

Hybrid

Roles & Responsibilities: • To be part of a highly skilled ASIC Team working on the newest technology nodes • Responsible for overall IP/Block and sub-system verification from test plan creation, SystemVerilog/ UVM testbench development to signoff • Ensure first pass product through multi-dimensional verification coverage including mixed mode verification • Mentoring and coaching junior team members • Pair with similar domain specialists across other geographical locations on core technical initiatives Skills required: • Should have expertise in IP/Block/Subsystem level verification and AMBA protocols-APB/AHB/AXI. • Proven track record of building test plan, UVM Environment and test benches ...

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