158 Ahb Jobs - Page 7

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Bachelors or Masters from Engineering Background and Preferably from IIT, NIIT or Top ranked Institutes. Minimum Qualifications:Strong coding experience in perl, python (one of the programming languages). Strong in system Verilog 3 + years' experience on AMBA protocols. Strong in computer architecture.Preferred Qualifications:Bringing up coherent protocols from 0 to1. 1-3 years of Experience on Network on Chip verification. 1-3 years of experience developing protocol checkers, bridge checkers, VIP integration, 1-3 Configurable IP verification. Strong background and experience on Coherent Protocols (IDI, CHI). Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES andPHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Bachelor in Electronics & communication Engineering, Computer Engineering, and/or Computer Science plus 4 to 6 years of relevant work experience, Masters in Electrical Engineering, Computer Engineering, and/or Computer Science plus 3 to 5 years of relevant work experience. Experience owning a testplan and executing to verification closure. 4 plus years of experience in SystemVerilog, OVM/UVM. Knowledge of AMBA protocols (AXI, AHB, APB). Knowledge of PCIe is a plus. Knowledge of power aware verification is a plus. Strong scripting skills. Excellent verbal and written communication skills. Exposure to Formal verification techniques is a plus. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 6+ years' experience-OR -a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 4+ years of experienceMandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving skills .Preferred skills :- BFM development , third party VIP integration , evaluation of VIP's , formal verification skills and c++ Preferred Protocol knowledge on PCIE , Cxl ,Solid verbal/written communication skills.o Effective team player with continuous learning mindset.Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Bachelor in Electrical Engineering, Computer Engineering, and/or Computer Science plus 12-14 years of relevant work experience, Masters in Electrical Engineering, Computer Engineering, and/or Computer Science plus 10-12 years of relevant work experience, or a PhD in Electrical Engineering, Computer Engineering, and/or Computer Science plus 8-10 years of relevant work experience. Experience owning a testplan and executing to verification closure. 5 plus years of experience in SystemVerilog, OVM/UVM. Knowledge of AMBA protocols (AXI, AHB, APB). Knowledge of PCIe is a plus. Knowledge of power aware verification is a plus. Strong scripting skills. Excellent verbal and written communication skills. Exposure to Formal verification techniques is a plus. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Experience in IP/Subsystem level Verification Good hands-on experience in verifying PCIe protocol (Gen4/Gen5/Gen6) Good knowledge on PCIe transaction layer, routing, reset flows etc Good experience with AXI protocol, NOC subsystem verification Good SV-UVM knowledge with hands-on experience in testbench development Good debugging skills Knowledge on performance verification is a plus.

Responsibilities As a CPU Verification Engineer, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems. Key Duties: Verification Environment Ownership:Take charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and Communication:Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Functional Verification Experience:Extensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies. Computer Architecture Knowledge:Good understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains. Multi-Processor Cache Coherency:Experience in verifying multi-processor coherency, cache designs and protocols and memory subsystems, ensuring seamless operation in complex systems. Strong programming skills:Proficiency in C++, Python scripting or similar languages. Preferred technical and professional experience Experience with Hardware Description Languages (HDLs):Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts. Experience in System-Level Verification:Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design. Minimum one full life cycle experience of a processor/SoC verification flow with focus Cache Coherency Verification. Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects