158 Ahb Jobs - Page 4

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. As a FPGA Verification Engineer at Nokia, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. This role typically requires 36 years of experience developing SystemVerilog UVM-based test environments and implementing comprehensive test plans at block, sub-chip and chip levels Strong proficiency in Hardware Verification Languages (HVL), with practical coding experience for verification tasks Practical experience using industry-standard simulators such as VCS, NC-Sim, or ModelSim (MTI), along with strong skills in waveform-based debugging. Solid understanding and practical application of UVM or similar modern verification methodologies. Experience with scripting languages such as Perl is highly valued and will help you stand out. It would be nice if you also had: Working knowledge of RTL design and familiarity with technologies like Ethernet, PCIe, and preferably telecom protocols. Strong analytical, troubleshooting, and problem-solving skills, with a structured and thorough approach to work. Good written and oral communication skills are required. Excellent written and verbal communication skills. Flexible, innovative, and self-driven team player with a strong willingness to take initiative. Design and develop comprehensive FPGA verification plans. Create and implement verification environments and testbenches. Develop and execute test scenarios for running simulations. Perform coverage analysis to ensure thorough verification. Provide lab support during FPGA and board bring-up phases. Collaborate closely with design and system teams to drive verification solutions. Independently manage verification tasks and projects. What We Offer: Opportunity to work in short product development cycles, allowing you to quickly see the real impact of your contributions on products and business success. International career development opportunities with internal mobility programs that encourage professional growth and advancement within the company. Access to a variety of social, wellness, and hobby clubs to support a balanced lifestyle and foster a sense of community. A friendly, inclusive, and supportive atmosphere where collaboration and mutual respect are core values. The chance to work alongside highly skilled, motivated, and innovative colleagues who are passionate about technology and excellence.

Experience: 6+ years of experience in pre-silicon RTL Verification /IP Verification / SOC verification, Strong knowledge of System Verilog and working knowledge of recent verification methodologie Required Candidate profile Notice Period: 0- 60 days Education: BE/ B.Tech/ Master degree in Electrical Engineering or Computer Science

Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead, guide, mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress, potential challenges encountered and milestones achieved to stake holders and team members Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 15 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 9 + years of experience in Functional Verification of processors or ASICs. Minimum 6+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading team. Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES andPHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification.

Design Verification Engineer (5+ years) ASIC/SoC/FPGA Design Verification (Bangalore, Chennai and Hyderabad) Design Verification with planning, architecture, development, maintenance, and execution on complex IPs and/or SOCs. Strong knowledge of digital design principles and computer architecture. Proficiency in verification languages like Verilog or SystemVerilog. Experience with UVM (Universal Verification Methodology).

Siplont Sytems Pvt Ltd is looking for SoC Verification Engineer to join our dynamic team and embark on a rewarding career journey. Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existing products or concepts to ensure compliance with industry standards, regulations, and company policies Preparing proposals for new projects, identifying potential problems, and proposing solutions Estimating costs and scheduling requirements for projects and evaluating results

Key Responsibilities Work closely with design team to review the design spec and define/participate detailed testplan Strategy and verification plan Develop testbench at SOC level for complex ASIC System-On-Chips Develop and maintain verification environment in UVM Implementation verification including Scan, JTAG related logic. Develop and improve the verification flow and methodology Maintain regression and debug test failures with designers Requirements : B. Tech /BE/ME/M Tech in Computer Science, Electronics/Electrical Engineering or related fields with 2 - 10 years of relevant hands-on experience. Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology) Experience in Unit and SoC Verification, JTAG insertion. Deep understanding of modern verification concepts. Good scripting skills in languages such as Perl, Tcl, or Python. Programming skills in System Verilog, C, C++ Working knowledge of RTL coding in Verilog, Synthesis STA Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Excellent written and verbal communication skills.

SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu or Haps) Understanding of JTAG based debuggers Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Proficient in RTL design using Verilog/SystemVerilog or VHDL In-depth knowledge of FPGA architecture and development flows (synthesis, P&R, timing analysis) Familiarity with high-speed interfaces and protocols like PCIe, Ethernet, DDR, AXI, AHB, SPI Required Candidate profile Experience with debugging tools like ChipScope, SignalTap, Logic Analyzer Proficiency in scripting languages like Python, Tcl, or Perl for automation of FPGA workflows

Knowledge on verification plans based on design specifications and requirements Proficiency in UVM and SystemVerilog for developing verification environments Unterstanding of protocols like PCIe, USB, Ethernet, or AMBA (AXI, AHB, APB) Required Candidate profile Hands-on experience with debugging tools like Verdi, DVE, or SignalTap Ability to analyze and resolve complex design and verification issues Proficiency in scripting languages like Python, Perl, Shell

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 4 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 4+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Monitoring and improve existing simulation environments and simulation efficiency. Good to Have: Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during micro architects development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role The graphics GT validation team is responsible for validating industry-leading GPU (3D, Media, Compute) hardware intellectual property (IP) blocks and system-on-a-chip (SoC) products for discrete graphics and throughput computing. We strive to lead the industry through continuous innovation and world-class engineering. We work closely with partners across Intel and do not let any organizational boundary get in the way of solving problems. We are looking for a GPU Design Verification Engineer to join our team. In this position you will help us with the following responsibilities Pre-silicon verification and content development of Intel's GPU IP, with focus on 3D/Compute pipelines and Memory Fabric. Engaged in the full lifecycle of verification from planning to test execution. Closely interface with architecture and design teams to understand design product requirements and develop comprehensive test plans and test content. Conduct, participate in test plan, test reviews, develop verification tests, their execution, debug, and triage of failures. The ideal candidate will have the following skills in addition to the qualifications listed below. Thoughtful and perceptive analytical skills A genuine curiosity for understanding the system Be dedicated and committed to creative problem solving and getting things done Strong verbal and written communication skills and Work well in a team environment Qualifications Btech/BS and Ms/MTech in Electrical Engineering, Computer Engineering, Electronics, or related field. BTech/BS with minimum 3 years of experience or Ms/MTech with Minimum 1 Year experience in the above-mentioned specializations.Your experience should be in the following areas Strong background in Pre-Si verification. Strong background in Logic Design and Architecture. Experience with a design simulator, functional coverage concepts and implementation, test development, execution, and debug. Working knowledge of SV assertions, Coverage Point coding.Development and execution of validation test plans. Familiarity of C/C++ languages and experience in software development using any of these languages is an added advantage Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

As a CPU Verification Engineer, you will play a pivotal role in the pre-silicon functional and performance verification of our cutting-edge chipsets. Your responsibilities will cover a spectrum of critical areas, including the cache/nest subsystem, interrupt, memory hierarchy, and various on-silicon IP integral to our upcoming IBM Power Systems offerings. Leveraging state-of-the-art techniques, you will be at the forefront of simulating and validating the designs of these bespoke microprocessor-based systems. Key Duties: Verification Environment OwnershipTake charge of the verification environments for microprocessor components, contributing significantly to the identification of functional and performance issues before silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes. Documentation and CommunicationThoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Communicate progress effectively, keeping team members and stakeholders informed of milestones achieved and potential challenges encountered. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Functional Verification ExperienceExtensive experience in functional verification of processors, demonstrating a deep understanding of verification methodologies. Computer Architecture KnowledgeGood understanding of computer architecture, including Processor core design specifications, Coherency and Cache Designs, Processor IO subsystem, Interrupt architecture, with expertise in at least any one of the above domains. Multi-Processor Cache CoherencyExperience in verifying multi-processor coherency, cache designs and protocols and memory subsystems, ensuring seamless operation in complex systems. Strong programming skillsProficiency in C++, Python scripting or similar languages. Preferred technical and professional experience Experience with Hardware Description Languages (HDLs)Proficiency in hardware description languages like Verilog and VHDL and general computational logic design and verification concepts. Experience in System-Level VerificationExposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design. Minimum one full life cycle experience of a processor/SoC verification flow with focus Cache Coherency Verification. Knowledge of system-level architecture including buses like AXI/ACE/CHI, AMBA interconnects

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.This posting is for a position on the DMR IMH OOB Validation Team. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience with validation in both simulation and emulation environments. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Role and Responsibilities You will be part of Intel Core Design Team driving Intel's latest CPUs in the World's leading process technologies. Develops pre-Silicon functional verification tests to verify system to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify test bench and tests. We're looking for a highly motivated, Pre-Silicon Verification Engineer who is responsible to ensure: Development of Complex Pre-Silicon Verification environment Development of Verification Components and coverage plans Write and execute validation Plans to ensure Right First Time Success of our Products Work directly with hardware architects, logic designers to influence overall SoC and system design. Qualifications Qualifications Candidatemust possess a master's degree in Electronics or Computer Engineering with at least 8+ or more years of experience in related field. Preferred Qualifications: Experience in Processor verification Experience with Specman/SV Language is plus Experience in verifying Power Mgmt, Cache controllers and memory features is plus Experience with Formal verification techniques is a plus Strong background in scripting- PERL/Python System hardware and software debug skills Understanding of software and/or hardware validation techniques Solid understanding of system and processor architecture, and the interaction of computer hardware with software. Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills. Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core „¢, and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.

**Verification Planning and Execution*: 2. Develop and execute comprehensive verification plans. 3. Close verification with coverage closure, ensuring high-quality results. 4. Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions. 5. **Testbench Development*: 6. Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages. 7. Implement reusable Verification IP (VIP) components. 8. Collaborate with third-party VIP providers. 9. Developing vertically and horizontally re-usable test-benches 10. **Methodology and Flows*: 11. Demonstrate a solid understanding of ASIC design and verification methodologies. 12. Apply object-oriented programming principles effectively. 13. Implement constraint random verification methodology. 14. **Technical Skills*: 15. Proficiency in SystemVerilog (OVM/UVM) and other relevant languages (C/C++, Perl, Tcl, Python, Verilog PLI, SV/DPI) 16. Familiarity with industry standards (e.g., I2C/SPI/AHB). 17. Gate level simulation 18. Experience with low-power verification using UPF (Unified Power Format) is a plus. 19. Knowledge of formal verification techniques is advantageous. 20. **Collaboration and Communication*: 21. Work effectively with internal teams and external customers. 22. Strong written and verbal communication skills. 23. Initiative, analytical problem-solving abilities, and adaptability within a diverse team environment.

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

Being part of DCS group, candidate will be working on PCIe, CXL based Switches, Re-timers and flash controllers for data-centers. Responsibilites: Create Micro-Architecture Specification. Work with team members to design RTL and provide support to verification. Work on constraint development for CDC, RDC and synthesis. Review Test plans from Verification team. Support Emulation and Firmware team in bringup. Qualifications/Requirements Qualifications/Requirements Minimum B.Tech/M.Tech in Electronics or related field. 10+ years of experience in RTL Design and timing aspects of IC design, with leadership capability. Key Skills: Expertise in VLSI logic design, understanding architecture and design planning. Expertise in synthesis/debugging, and timing closure. Knowledge of protocols like PCIe, CXL, AXI, AHB, I3C etc. Proficiency in Tcl and Perl scripting. Power planning and implementation techniques. Proficiency in CDC, RDC and constraint development. Excellent debugging, analytical, and leadership skills. Strong communication skills and interpersonal abilities.

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Lead the development of the verificationplans,environment, testbenches and writing testcasesfor theCacheCoherency TransportInterconnectFabric in IBM Server Processors. Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 9+ years of experience in Functional Verification of processors or ASICs. 3+years of experience inthe followingareas Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processorCacheCoherency/Network on Chip/MemoryHierarchyverification. AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabricinterfaceverification or any otherProcessor/SoC coherency transport interconnectfabric verification. Minimum one full life cycle leadership experience of a processor/SoC verification flowwith focus on Coherency Transport Interconnectand/or Network on ChipVerification Good object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl. Verification knowledge inClock domain crossing and reset domaincrossing Knowledge of functional verification methodology likeUVM/OVM Knowledge of HDLs (VHDL/Verilog) Developed testplans and test strategies for IP/unit/block level verificationof Coherency Transport Interconnects Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure.

About The Role Architects, develops and integrates layered Verification IPs, testbenches, testplans and test suite to validate the integrity and quality of Verification IPs and compliance with standards and SoC architecture & micro-architecture requirements. Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and conform to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation testbenches and test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Experience in PreSilicon Performance Verification OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 2+ years' experience on AMBA protocols. Strong background and experience on Coherent Protocols (IDI, CHI). Strong coding experience in perl, python (one of the programming languages). Strong in coherency architecture. Preferred Qualifications: Bringing up coherent protocols from 0 to1. 2 + years of Experience on Network on Chip verification. 2+ years of experience developing protocol checkers, bridge checkers, VIP integration, Configurable IP verification. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience. Related technical experience should be in/withSilicon Design and/or Validation/Verification.Preferred Qualifications Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. Proficiency in UVM/SV constrained-random coverage based design verification. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. UVM/SV Verification IP architecture, development and validation experience. Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Experience with one or more scripting languages to facilitate automation. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.