7 Advanced Nodes Jobs

As a Physical Verification Engineer at Digicomm Semiconductor Private Limited, you will be responsible for the following key responsibilities: - Design Rule Checking (DRC): You will run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. - Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. - Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC ...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Job Requirements Roles & Responsibilities Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC/ASIC designs. Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC/LVS/Antennas etc.). Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis. Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies). Handle STA (Static Timing Analysis) using tools like PrimeTime/Tempus and drive closure. Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively. Experience in synthesis and formal equivalence checking (LEC) to ens...

Physical design engineers - MNC BULK HIRE - 100% WFH MUST: 7 t0 14 YEARS AS physical design engineer MUST: 7+ years of experience in ASIC physical design , Strong with industry-standard tools (e.g., Innovus, ICC2, PrimeTime, Voltus, Calibre) Required Candidate profile Solid understanding of timing, signal integrity, IR drop, and physical verification Good scripting skills (TCL, Python, or Perl) for flow automation EXP with advanced nodes & UPF WHATSAPP@9108687980

As a highly motivated and innovative digital design engineer at Synopsys, you will play a crucial role in driving the innovations that shape the future in the Era of Pervasive Intelligence. Your expertise in ASIC design methodology and flows, particularly focusing on low power analysis and optimization, will be instrumental in empowering the creation of high-performance silicon chips and software content. With a proven track record in working with advanced nodes, especially at 5nm and below, you will be responsible for developing and driving digital design methodologies to achieve the lowest power consumption. Your strong background in both digital and physical design, coupled with your prof...

As a Physical Verification Engineer at Digicomm Semiconductor Private Limited, you will be responsible for various crucial tasks to ensure the successful verification and validation of semiconductor designs. Your primary duties will include: Design Rule Checking (DRC): You will conduct DRC checks using industry-standard tools to identify any violations of manufacturing design rules. It will be essential for you to collaborate closely with layout designers to address and resolve any identified DRC issues effectively. Layout vs. Schematic (LVS) Verification: You will be tasked with performing LVS checks to verify the accurate alignment between the physical layout and the schematic design. Your...

Job Description: We are seeking an experienced Physical Design Engineer with strong expertise in VCLP (Voltage-Controlled Low Power) techniques and full flow RTL to GDSII implementation. Key Responsibilities: End-to-end ownership of physical design flow from RTL to GDSII VCLP implementation and optimization (highly important) Block-level and full-chip physical design Perform timing analysis , DRC/LVS checks , and power optimization Collaborate with front-end, verification, and DFT teams for successful tape-out Must-Have Skills: Strong hands-on experience in VCLP RTL to GDSII implementation EDA tools (Cadence Innovus, Synopsys ICC2, PrimeTime, Mentor Calibre) Scripting languages: Python, TCL,...