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9.0 - 11.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Job Requirements 9-10 years experience with Bachelor's degree in Electronics Engineering or equivalent Good experience in Physical Design with innovus tool Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5/3nm Strong leadership skills to ...
Posted 1 day ago
4.0 - 9.0 years
15 - 20 Lacs
hyderabad, bengaluru
Work from Office
Educational Background • BE or MTech in Electronic/VLSI Engineering • 4 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm/16nm Finfet & 5+ exp **** TSMC 3nm Exp - MANDATORY. POINTERS TO BE CONSIDERED: 1. Candidate needs to be very clear about basic concepts. 2. He/She is expected to be really good at problem solving. 3. The candidate has to be able to challenge traditional way of doing layouts (Out of the box approach is needed). 4. Candidate needs to be able to work independently with minimal inputs. 5. Dedication, commitment and flexibility are very critical to achieve tight timelines without compromising
Posted 4 days ago
5.0 - 10.0 years
15 - 20 Lacs
hyderabad, bengaluru
Work from Office
Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items....
Posted 1 week ago
4.0 - 9.0 years
15 - 20 Lacs
Hyderabad
Work from Office
Role & responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & rev...
Posted 4 months ago
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