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5 - 8 years

4 - 9 Lacs

Hyderabad

Hybrid

Required skill :Semiconductor Layout Development, CAD Tool Proficiency, Layout Verification, Standard Cell, Analog, Mixed-Signal, and Custom Digital Block Layouts Advanced CMOS Process, Layout Library Development, standard cell layout library developments. Physical Verification, Layout Optimization, Design Rules, Yield, and Reliability, Layout Fundamentals, Schematic Understanding, Layout Effects on Circuit, Cadence Virtuoso and Mentor Caliber Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques Problem-Solving: Excellent problem-solving skills in physical verification. Teamwork and Communication: Ability to work in a team and communicate effectively. Guiding junior team members

Posted 2 months ago

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Synthesis & STA (Static Timing Analysis) Randstad

6 - 11 years

25 - 40 Lacs

Noida

Hybrid

We are seeking a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team . This role requires strong analytical skills, attention to detail, and collaboration with cross-functional teams . Proficiency in EDA tools and digital design principles is essential. Location: Noida (Hybrid 3 days work in office) Experience: 6 to 15 years Key Responsibilities & Skills: Work with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes (3nm, 5nm, 16nm). Strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff . Experience with EDA tools such as Genus, Fusion Compiler, PrimeTime, Tempus, Conformal . Strong scripting skills in Perl, TCL, Python for automation and flow development. To apply, click on the Apply option or share your resume with Heena at heena.k@randstad.in

Posted 3 months ago

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Physical Verification and Closure Exiger Technologies

5 - 8 years

20 - 30 Lacs

Bengaluru

Work from Office

Key Responsibilities: Physical Verification closure for Arm CPU implementation. Multiple tape-outs completed with a strong focus on Physical Verification closure. Deep understanding of DRC/LVS/PERC/Antenna/DFM and associated concepts for advanced nodes on TSMC and Samsung foundries. Experience with running Physical Verification on Arm CPU designs for advanced technology nodes. Expertise in fixing issues related to DRC/LVS/PERC/Antenna/DFM on base/metal layers and recommending appropriate fixes for P&R tool flow. Strong knowledge of advanced technology nodes like Samsung Foundry (4nm/3nm) is a significant advantage.

Posted 3 months ago

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