5.0 - 10.0 years

7 - 17 Lacs

bengaluru

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IC Package Design Engineer Experience with Cadence APD IC Package Design experience with Cadence APD Good understanding of package/substrate design and package assembly rules related to flip chip designs. Exposure to different package technologies such as MCM, flip chip / wire bond, 3D, 2.5D etc., added advantage Expertise in High-Speed Complex Package and PCB designs with HDI, Blind and Buried Via technologies. Hands-on expertise with PCB designs involving High Speed Parallel Bus interfaces including DDR, GDDR and HSIO interfaces including PCIe, SERDES. Good Exposure to Stackup design, DFM, DFA rules and adherence. Should have expertise in constraint setting in layout tool.

Posted 1 week ago

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Soc Verification Engineer || SOC Validation Engineer Acesoft Labs

2.0 - 7.0 years

12 - 22 Lacs

hyderabad

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Job Description: We're looking for a verification SME, responsible for the SoC verification process and designing the next-generation HBM DRAM products. Deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration. Responsibilities: • Develop test plans at SOC Level and analyze Coverage. • Build verification environments to verify complex SOCs. • Develop Random/Directed test in RTL and GLS environments. • Review architectural specifications to ensure high quality. • Work with customers to understand their verification &validation requirements • Debug and identify root causes and solutions for pre-silicon and post-silicon is...

Posted 1 month ago

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