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STA Engineer Capgemini

3.0 - 7.0 years

7 - 11 Lacs

hyderabad

Work from Office

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks ...

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