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10.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience with design and multi power domains with clocking. Experience in verilog or system verilog language. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in STA closure, DV test-plan review and coverage analysis of the sub-system and chip level verification. Knowledge of process cores, interconnects, debug and trace, security, interrupts, clocks/reset, power/voltage domains, or pinmuxing. A...

Posted 6 days ago

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