Posted:1 week ago|
Platform:
On-site
Full Time
Hi All,
Block / Subsystem / Partition / Full chip.
Role: Synthesis and Timing Constraint Engineer.
EDA Tool: Cadence Genus & Fishtail.
Node: TSMC 3nm / 5nm.
UPF Implementation hands-on is must.
Synthesis PPA optimization, Hierarchical partition synthesis, Lint, Sanity Checks.
Timing constraints generation and validation.
Tcl, Perl, Python Scripting mandatory.
Eximietas Design
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