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Happiest Minds Technologies
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SENIOR ENGINEER - DEVELOPER

Posted 7 months ago. This role may no longer be accepting applications.

SENIOR ENGINEER - DEVELOPER

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Happiest Minds Technologies

3 - 5 years

Bengaluru

Posted:7 months ago

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Job Description

Role:
FPGA Design Engineer
Location:
Bangalore
3 to 5 Years of experience in Develop RTL microarchitecture and design based on specifications
Develop RTL for high speed and low latency designs, integrate IPs from different FPGA vendors
Implement RTL (Verilog/VHDL/SystemVerilog)
Perform module level simulation, perform integration and synthesis of RTL designs
Implement on FPGA boards and validate the performance
Collaborate with verification, and firmware teams to ensure end-to-end integration and functionality
Support bring-up and on-board validation as required

Skills Required

c++ electronics xilinx digital design vhdl verilog hdl rtl design axi fpga modelsim design rtl coding perl system verilog xilinx ise matlab asic sta asic verification vlsi design c rtl engineering uvm verilog asic design fpga design vlsi

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Job Type

Full Time

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