Senior Design Verification Engineer

As a Senior Design Verification Engineer, you will be responsible for the following tasks: - Developing SV / UVM test benches and coding test cases - Analyzing and closing code and functional coverage - Collaborating with the team to achieve verification closure - Utilizing experience with Python or any other scripting language, which is considered a plus - Having working knowledge of bus protocols such as AXI, APB, UART, and IJTAG protocols, which is an advantage You should have 4 to 6 years of experience in this field. The location for this position is Hyderabad. As a Senior Design Verification Engineer, you will be responsible for the following tasks: - Developing SV / UVM test benches and coding test cases - Analyzing and closing code and functional coverage - Collaborating with the team to achieve verification closure - Utilizing experience with Python or any other scripting language, which is considered a plus - Having working knowledge of bus protocols such as AXI, APB, UART, and IJTAG protocols, which is an advantage You should have 4 to 6 years of experience in this field. The location for this position is Hyderabad.