We are seeking a Director of Engineering (Design Verification) to oversee and expand our DV practice. With over 15 years of experience in SoC/ASIC verification, exceptional technical expertise, demonstrated leadership abilities, and the talent to motivate high-performing teams, you will play a pivotal role in our organization. Responsibilities include leading end-to-end SoC/ASIC Design Verification programs, establishing DV methodologies, flows, and best practices (UVM, SV, C-based), delivering technical leadership and practical problem-solving, managing and guiding top-performing engineering teams, collaborating with cross-functional teams for project success, driving customer engagement, ensuring delivery excellence, and supporting business development through pre-sales and technical discussions. The ideal candidate will possess a minimum of 15 years of semiconductor design verification experience, including at least 5 years in a leadership capacity. Proficiency in SystemVerilog, UVM, C/C++ co-simulation, and testbench architecture is essential. In-depth knowledge of ARM architecture, AMBA protocols (AXI, CHI, APB), high-speed interfaces (PCIe, DDR, Ethernet), Formal Verification, GLS, coverage closure, GLS methodology/flows, VIP Integration & Sequence usage, C-SV co-simulation, and Python scripting is required. Strong skills in people management, mentoring, and stakeholder engagement are also critical. Joining Seminovaa offers you the chance to be part of a rapidly growing semiconductor services company, led by its founder. You will have the opportunity to shape and lead the Design Verification practice, working on cutting-edge projects in AI, Automotive, Networking, and High-Performance Computing. Our collaborative, innovation-driven culture provides global exposure and a dynamic work environment. Apply now by sending your profile to careers@seminovaa.com. #SemiconductorJobs #VLSICareers #ChipDesign #NowHiring #Seminovaa #DFTengineers #Verificationengineers #PhysicalDesignEngineers,
As a Senior/Lead Engineer in Bengaluru, India, you will need a minimum of 35/57 years of industry experience, respectively. Your educational background should include a B.E./B.Tech in Electronics, Electrical, Electronics & Communication, or related field, while a preferred qualification would be an M.E./M.Tech in VLSI Design, Microelectronics, or a related specialization. Candidates from semiconductor service or product companies are welcome, with a strong emphasis on hands-on expertise in Physical Design and EDA tool flows. Your responsibilities will revolve around owning the end-to-end Physical Design flow, including floorplanning, placement, CTS, routing, ECOs, IR drop analysis, and physical verification. You will drive Static Timing Analysis (STA) closure across PVT corners, script automation in Tcl/Perl to optimize workflows, and collaborate with various teams for smooth integration. Experience with Synopsys or Cadence EDA tools and contribution to AI-assisted PD automation initiatives will be expected. We are looking for individuals with proven experience in ASIC Physical Design and STA, strong scripting skills (Tcl, Perl; Python a plus), and deep knowledge of PD sign-off flows, IR drop, clock tree optimization, and ECOs. Exposure to multiple foundry nodes, particularly FinFET, is advantageous. A problem-solving mindset with a focus on first-time-right execution is essential. Candidates from product companies or service firms are encouraged to apply. Joining Seminovaa offers you a core team role with direct impact and ownership, the opportunity to work on global, high-impact projects alongside industry veterans, and a combination of startup agility and deep-tech challenges that can accelerate your career growth. Our employee-first culture prioritizes flexibility, transparency, and respect for your work-life balance. If you meet these qualifications and are excited about the prospect of working with us, send your profile to careers@seminovaa.com and take the first step towards a rewarding career opportunity.,