RTL

As an RTL Design Engineer at HCL Tech, you will be a vital team member involved in the design and development of advanced ASICs/SoCs. Your role will encompass the entire RTL design process, from initial concept to coding, verification, integration, and ensuring successful tape-out. You will collaborate closely with various teams to drive the next-generation chip design. Your responsibilities will include developing RTL code for intricate digital circuits using HDLs like Verilog or VHDL, conducting thorough functional verification through simulation and formal methods, ensuring compliance with coding standards during code reviews, analyzing timing performance, and engaging in static timing analysis. Additionally, you will keep abreast of the latest RTL design methodologies and tools to enhance your design capabilities. To qualify for this position, you should hold a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (a Master's degree is advantageous) and possess over 5 years of hands-on experience in RTL design for ASICs/SoCs. Your expertise should extend to designing and verifying complex digital circuits, proficiency in Verilog or VHDL, familiarity with verification methodologies such as UVM, and a solid grasp of digital design concepts including combinational logic, sequential logic, and state machines. Experience with SDC format for timing closure and scripting languages like Python or Perl will be beneficial. At HCL Tech, you can expect a competitive salary and benefits package, the chance to work on cutting-edge technologies, a collaborative and dynamic work environment, and ample opportunities for professional growth and development. Join us in shaping the future of chip design and make a significant impact in the semiconductor industry.,