R&D Engineering, Staff Engineer

Job Description

Develop and maintain automation scripts for CAD tools using languages like Python, Perl, or TCL. Collaborate with designers and engineers to identify automation opportunities and implement solutions. Design and implement automation frameworks for design flow of multiple functions using AI. Proficient in troubleshooting and debug automation scripts and CAD tool issues. Develop and maintain documentation for automation scripts and processes. Understanding of DV flow and generating test benches and test cases. Understanding RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Understanding CAD infrastructure, methodology will help to setup project environment. Contribute to enhance quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support Internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty etc and other frontend views will add value to this position. Writing RTL Code, Solid Verilog, PERL, and Python skills and TCL are good additions. Understanding static timing analysis and synthesis, DFT/ATPG skills would be a plus. Previous knowledge of customer support and/or silicon bring-up is a plus. Drive automation to enhance IP Quality-Assurance flow & Release process. Define and establish a comprehensive QA process for IP development. Integrate new features and functionalities into IPQA scripts with automation team. Streamline the release process to reduce cycle time and improve efficiency. Automate release tasks, such as packaging and documentation, to reduce manual errors. Improve release quality by integrating QA processes into the release workflow. Enhance releasing documentation to ensure completeness and accuracy. Validate the integrity of the release package by checking for corruption, tampering, or other issues (Time Stamp and Locking Source of Release package and Release package itself). Required Skills: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.